| Week # |
Dates |
Lecture/Lab Topic |
Due Date |
1
Aug. 23 & 25
Course and WARP Overview
| ---
| | | |
2
Aug. 30 & Sept. 1
FPGA Design and Aloha Introduction
| Project Proposals Due 10/18, 11:59pm
| | | |
3
Sept. 6 & 8
Aloha Lab Walk-Through and Lab 1
| Due 9/12
| | | |
4
Sept. 13 & 15
System Generator Lecture and Lab 2
| Due 9/19
| | | |
---
---
Reminder: Project Proposals Due 10/18
| ---
| | | |
5
Sept. 20 & 22
Verilog and SysGen Lab in Verilog (Lab 3)
| Due 9/26
| | | |
6
Sept. 27 & 29
Physical Layer Coding and Lab 4
| Due 10/3
| | | |
7
Oct. 4 & 6
Carrier Sense Multiple Access (CSMA) and Lab 5
| Due 10/13
| | | |
8
Oct. 11 & 13
Fall Break (Tues.) and CSMA/Lab 5 (Thurs.)
| ---
| | | |
9
Oct. 18 & 20
CSMA w/ Collision Avoidance (CSMA/CA) and Lab 6 Part A
| Due 10/24
| | | |
10
Oct. 25 & 27
CSMA/CA and Lab 6 Part B
| Due 10/31
| | | |
11
Nov. 1 & 3
Rate Adaptation and Lab 7
| Due 11/7
| | | |
12
Nov. 8 & 10
Project Work Week 1 (Working In-Lab Meeting Req'd)
| Progress Reports Due 11/21, noon
| | | |
13
Nov. 15 & 17
Project Work Week 2 (Working In-Lab Meeting Req'd)
| ---
| | | |
14
Nov. 22 & 24
Project Updates (Tues.) and Thanksgiving (Thurs.)
| ---
| | | |
15
Nov. 29 & Dec. 1
Project Work Week 3 (Working In-Lab Meeting Req'd)
| Final Reports Due 12/7 noon
| | | |
16
Dec. 8 8-11am
Final Project Presentations
| ---
| | | |
|
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|
|
*This schedule is best-effort as of the beginning of the semester and subject to
change according to the time available in the semester.