Digital Systems Design

CSE/EE 5/7387 Digital Systems Design - Syllabus

Southern Methodist University, Fall 2016

Available help for the final project

These are walk-in hours available to ALL STUDENTS to get assistance on their project.

Regular T.A help desk hours

Monday November 28, 09:00AM to 11:00AM in Caruth 484
Thursday December 1, 11:00AM to 01:00PM in Caruth 484
Monday December 5, 09:00AM to 11:00AM in Caruth 484

Open lab sessions

Wednesday November 30, 02:00PM to 05:00PM in Junkins 215
Thursday December 1, 09:00AM to 10:50AM in Junkins 215
Friday December 2, 08:00AM to 11:50AM in Junkins 215
Tuesday December 6, 03:00PM to 05:00PM in Caruth 484
Wednesday December 7, 10:00AM to 01:00PM in Junkins 215

Feel free to come to any or all of the lab sessions

Schedules

Class schedule

Class	Day	Time	Location
	Mon	11:00AM-12:20PM	Junkins 113
	Wed	11:00AM-12:20PM	Junkins 113

Laboratory schedule

Sections	Day	Time	Location
N13C	Wed	3:00PM-4:50PM	Junkins 215
N12C	Thu	9:00AM-10:50AM	Junkins 215
N11C	Fri	8:00AM-9:50AM	Junkins 215
N15C	Fri	10:00AM-11:50AM	Junkins 215
N14C	-	Distance Students Only	No on-campus Laboratory meeting

Instructors

Class instructor

David Kebo Houngninou
Computer Science and Engineering Department
Bobby Lyle School of Engineering
Southern Methodist University
P.O. Box 750122
Dallas, TX 75275-0122
Office: Caruth Hall 308
Email: dhoungninou@smu.edu

Lab instructor

Yi Sun

Office: Caruth Hall 308
Email: yis@smu.edu

Help desk hours:
M 09:00AM-11:00AM
Th 11:00AM-01:00PM
Caruth Hall 484

Office hours

MW 10:00AM-10:50AM
Caruth Hall 308
or by email appointment

Material

Text

Introduction to Logic Synthesis Using Verilog HDL, Robert B. Reese and Mitchell A. Thornton, Morgan & Claypool Publishers , 2006, ISBN 10-1598291076 (errata).
Finite State Machine Datapath Design, Optimization, and Implementation, Justin Davis and Robert B. Reese, Morgan & Claypool, 2008, ISBN 1-59829-529-2.
Fundamentals of Digital Logic with Verilog Design, 2nd Edition, Stephen Brown and Zvonko Vranesic, Mc-Graw-Hill, 2007, ISBN 0-07-721164-2.

Software Downloads

Altera Quartus II Web Edition
Altera Quartus II Web Edition (v. 9.1)
Quartus II Handbook Volume 1: Design and Synthesis

Note that in the laboratory and on the machines on campus, we are using the Professional Version of QuartusII which is version 5.0.

Videos

IC Fabrication, 38:30, (.avi, .mp4, .wmv)
PN Junctions, 10:36, (.avi, .mp4, .wmv)
MOSFETs, 8:27, (.avi, .mp4, .wmv)
CMOS Logic Gates, 8:47, (.avi, .mp4, .wmv)
Packaging, 5:35, (.avi, .mp4, .wmv)

Topics

Digital Logic Design Review
HDL (Discrete Event) Simulators
Verilog Hardware Description Language (HDL)
Combinational Logic Synthesis using Verilog
Programmable Logic Architecture and LPMs
Timing Constraints and Timing Models in Programmable Logic
Pipelining for Increased Throughput
Sequential Logic Synthesis using Verilog
FSM State Assignment
High Level Synthesis

Learning management system

Announcements, grades, discussion board etc.: Canvas

References

HDL Chip Design, Douglas J. Smith, Doone Publications, 5th Edition, 1996, ISBN 0-9651934-3-8
Verilog tutorial

Course requirements

Prerequisites:
CSE 3381 - Digital Logic Design or EE 2381 Digital Computer Logic
Co-requisite:
Digital Systems Design Laboratory Enrollment

Class Schedule

WEEK	DATE	EVENTS/HOLIDAYS	OTHER CLASS NOTES	CLASS TOPIC AND OVERHEADS
Week 1	22-Aug	First Day of Class	NO LAB THIS WEEK	Introduction to Class and Altera Quartus2
	24-Aug		NO LAB THIS WEEK Reading Assignment Chapter 1 (Reese/Thornton)	Combinational Logic Review - Part 1
Week 2	29-Aug		LABORATORY 0: Quartus2 Tutorial Checklist	Combinational Logic Review - Part 2
	31-Aug		LABORATORY 0: Quartus2 Tutorial Checklist	Sequential Logic Review - Part 1
Week 3	05-Sep	NO CLASS SMU HOLIDAY	NO LAB THIS WEEK	NO CLASS SMU HOLIDAY
	07-Sep	Last Day to Request Excused Absence for Observance of a Religious Holiday	NO LAB THIS WEEK	Sequential Logic Review - Part 2
Week 4	12-Sep		LABORATORY 1: Schematic Capture Checklist	Event Driven Simulation
	14-Sep		LABORATORY 1: Schematic Capture Checklist	Event Driven Simulation
Week 5	19-Sep		LABORATORY 2: Combinational Logic Using HDL Checklist	Verilog Introduction for Combinational Logic - Part 1
	21-Sep		LABORATORY 2: Combinational Logic Using HDL Checklist	Verilog Introduction for Combinational Logic - Part 1
Week 6	26-Sep		LABORATORY 3: LPM Usage in Schematic Capture Checklist Notes	Verilog Introduction for Combinational Logic - Part 2
	28-Sep		LABORATORY 3: LPM Usage in Schematic Capture Checklist Notes	Verilog Introduction for Combinational Logic - Part 2
Week 7	03-Oct		NO LAB THIS WEEK	Implementation Technology Test 1 Review and sample problems
	05-Oct	Last Day to Change Majors before next Semester Enrollment	NO LAB THIS WEEK	Test 1
Week 8	10-Oct	Fall Break NO CLASS	LABORATORY 4: LPM Usage in Structural HDL Checklist	Implementation Technology
	12-Oct		LABORATORY 4: LPM Usage in Structural HDL Checklist	FPGA Architecture
Week 9	17-Oct		LABORATORY 4 (Extended): LPM Usage in Structural HDL Checklist	FPGA Architecture
	19-Oct		LABORATORY 4 (Extended): LPM Usage in Structural HDL Checklist	FPGA Architecture
Week 10	24-Oct		LABORATORY 5: Design Timing Analysis Checklist Notes	Timing in Digital Systems
	26-Oct		LABORATORY 5: Design Timing Analysis Checklist Notes	Timing in Digital Systems
Week 11	31-Oct		LABORATORY 6: Bit-level Pipelining Checklist Web Based Datasheets Altera Xilinx Cypress Actel Atmel Reading Assignment Chapter 2: (Reese/Thornton)	FPGA Timing and Data Sheets and Device Packaging
	02-Nov	Friday Nov 4: Last Day to Drop a Course	LABORATORY 6: Bit-level Pipelining Checklist Web Based Datasheets Altera Xilinx Cypress Actel Atmel Reading Assignment Chapter 2: (Reese/Thornton)	Bit-Level Pipelining
Week 12	07-Nov		LABORATORY 7: Controller Specification and Synthesis Using HDLs Checklist	FSMD Design
	09-Nov		LABORATORY 7: Controller Specification and Synthesis Using HDLs Checklist	Algorithmic State Machine Charts
Week 13	14-Nov		LABORATORY 8: Datapath/Synchronous Controller Design Checklist Lab 8 debugging notes	Controller Specification using HDL Test 2 Review Test 2 Review Solution
	16-Nov		LABORATORY 8: Datapath/Synchronous Controller Design Checklist Lab 8 debugging notes	Test 2
Week 14	21-Nov		FINAL PROJECT: Matrix Multiplier Cummings Paper on Blocking and Non-blocking Statements in Verilog	Resource Estimation and Scheduling
	23-Nov		NO LAB THIS WEEK	NO CLASS
Week 15	28-Nov		FINAL PROJECT: Matrix Multiplier	System Level Pipelining Test 3 Review
	30-Nov			Test 3
	02-Dec		LABORATORY 8 Lab 8 report due on Canvas at: 11:59PM
Week 16	05-Dec	Last day of instruction	FINAL PROJECT: Matrix Multiplier Checklist	State Assignment
	07-Dec
FINAL PROJECT		Thursday 08-Dec (11:30AM-2:30PM) JUNKINS 215 Last day to demonstrate the final project FINAL PROJECT REPORT Due on Canvas at: 11:59PM	SMU Final Exam Schedule FINAL PROJECT REPORT Due on Canvas at: 11:59PM

Grading Policy

	Grade
Laboratory Exercises	40%
Test 1 (in-class)	15%
Test 2 (in-class)	15%
Test 3 (in-class)	15%
Final Project Report	15%

Note: Grades on labs/tests/final will range from 0-100.
However, the final class grade will be scaled to fit the above grading policy.
(1 lab point is not equal to 1 test point)

Lab Policy

Grading Policy Acknowledgement Form

Late Assignments

Unless a documented and legitimate reason is provided, all labs turned in late will automatically have 20% of the total possible points deducted for each lab period that has elapsed since the due date. As an example, a 100-point lab that was due on Wednesday but turned in on Thursday will be graded as normal and then 20 additional points will be deducted for being late.

All labs are due at the beginning of the lab period

Students who do not turn in labs or participate in the laboratory will not pass this class. You must attend and turn-in at least 80% of all laboratories to avoid receiving a failing grade.

Makeup Examinations

There will be no makeup examinations, a missed examination will result in 0% unless a valid and documented excuse is presented. If possible, students should provide such documentation before the examination date. In any event, notification must be provided within 2 class periods following the missed examination. In the case of a legitimate excuse for missing an examination, an alternative for making up this portion of total grade will be provided to the student.

Information

Disability Accommodations:

Students needing academic accommodations for a disability must first register with Disability Accommodations & Success Strategies (DASS). Students can call 214-768-1470 or visit http://www.smu.edu/Provost/ALEC/DASS to begin the process. Once registered, students should then schedule an appointment with the professor as early in the semester as possible, present a DASS Accommodation Letter, and make appropriate arrangements. Please note that accommodations are not retroactive and require advance notice to implement.

Religious observance

Religiously observant students wishing to be absent on holidays that require missing class should notify their professors in writing at the beginning of the semester, and should discuss with them, in advance, acceptable ways of making up any work missed because of the absence. (See University Policy No. 1.9.)

Excused absences for university extracurricular activities

Students participating in an officially sanctioned, scheduled University extracurricular activity should be given the opportunity to make up class assignments or other graded assignments missed as a result of their participation. It is the responsibility of the student to make arrangements with the instructor prior to any missed scheduled examination or other missed assignment for making up the work. (University Undergraduate Catalogue)