CSE/EE 5/7387 Digital Systems Design - Syllabus

Southern Methodist University, Fall 2017

Available help for the final project

These are walk-in hours available to ALL STUDENTS to get assistance on their project.
Please take advantage of these resources to complete your project early.

T.A help desk hours

Monday November 20, 02:00 PM to 04:00 PM in Caruth 484
Tuesday November 21, 03:00 PM to 05:00 PM in Caruth 484
Tuesday November 28, 03:00 PM to 05:00 PM in Caruth 484
Wednesday November 29, 12:30 PM to 02:00 PM in Caruth 308
Wednesday November 29, 03:00 PM to 05:00 PM in Caruth 484
Friday December 1st, 08:00 AM to 11:50 AM in Junkins 215
Monday December 4th, 12:30 PM to 02:00 PM in Caruth 484
Wednesday December 6th, 11:00 AM to 02:00 PM in Junkins 215

Finite State Machine Design

Schedule

Class schedule

Class Day Time Location
Mon 11:00AM-12:20PM Caruth Hall 379
Wed 11:00AM-12:20PM Caruth Hall 379

Laboratory schedule

Sections Day Time Location
N13C Wed 3:00PM-4:50PM Junkins 215
N12C Thu 9:00AM-10:50AM Junkins 215
N11C Fri 8:00AM-9:50AM Junkins 215
N15C Fri 10:00AM-11:50AM Junkins 215
N14C - Distance Students Only No on-campus Laboratory meeting

Instructors

Class instructor

David Kebo Houngninou
Computer Science and Engineering Department
Bobby Lyle School of Engineering
Southern Methodist University
P.O. Box 750122
Dallas, TX 75275-0122
Office: Caruth Hall 308
Email: dhoungninou@smu.edu

Lab instructors

David Kebo Houngninou
&
Yi Sun

Office: Caruth Hall 308
Email: yis@smu.edu

Help desk hours:
T 01:00PM-03:00PM
Th 03:00PM-05:00PM
Caruth Hall 484

Office hours

MW 10:00AM-10:50AM
Caruth Hall 308
or by email appointment

Material

Text

Software Downloads

Altera Quartus II Web Edition (v. 9.1)
Quartus II Handbook Volume 1: Design and Synthesis

Note that in the laboratory and on the machines on campus, we are using the Professional Version of QuartusII which is version 5.0.

Videos

Topics

  • Digital Logic Design Review
  • HDL (Discrete Event) Simulators
  • Verilog Hardware Description Language (HDL)
  • Combinational Logic Synthesis using Verilog
  • Programmable Logic Architecture and LPMs
  • Timing Constraints and Timing Models in Programmable Logic
  • Pipelining for Increased Throughput
  • Sequential Logic Synthesis using Verilog
  • FSM State Assignment
  • High Level Synthesis

Learning management system

Announcements, grades, discussion board etc.: Canvas

References

  • HDL Chip Design, Douglas J. Smith, Doone Publications, 5th Edition, 1996, ISBN 0-9651934-3-8
  • Verilog tutorial

Course requirements

Prerequisites:
CSE 3381 - Digital Logic Design or EE 2381 Digital Computer Logic
Co-requisite:
Digital Systems Design Laboratory Enrollment

Class Schedule

WEEK DATE EVENTS/HOLIDAYS OTHER CLASS NOTES CLASS TOPIC AND OVERHEADS

Week 1

21-Aug

First Day of Class

NO LAB THIS WEEK

Introduction to Class and Altera Quartus2

23-Aug

NO LAB THIS WEEK

Reading Assignment Chapter 1 (Reese/Thornton)

Combinational Logic Review - Part 1

Week 2

28-Aug

LABORATORY 0: Quartus2 Tutorial

Combinational Logic Review - Part 2

30-Aug

LABORATORY 0: Quartus2 Tutorial

Sequential Logic Review - Part 1

Week 3

04-Sep

NO CLASS SMU HOLIDAY

LABORATORY 1: Schematic Capture

Checklist

NO CLASS SMU HOLIDAY

06-Sep Last Day to Request Excused Absence for Observance of a Religious Holiday

LABORATORY 1: Schematic Capture

Checklist

Sequential Logic Review - Part 2

Week 4

11-Sep

LABORATORY 1: Schematic Capture

Checklist

Event Driven Simulation

13-Sep

LABORATORY 1: Schematic Capture

Checklist

Event Driven Simulation

Week 5

18-Sep

LABORATORY 2: Combinational Logic Using HDL

Checklist

Verilog Introduction for Combinational Logic - Part 1

20-Sep

LABORATORY 2: Combinational Logic Using HDL

Checklist

Verilog Introduction for Combinational Logic - Part 1

Week 6

25-Sep

LABORATORY 3: LPM Usage in Schematic Capture

Checklist

Notes

Verilog Introduction for Combinational Logic - Part 2

27-Sep

LABORATORY 3: LPM Usage in Schematic Capture

Checklist

Notes

Verilog Introduction for Combinational Logic - Part 2

Week 7

02-Oct

LABORATORY 4: LPM Usage in Structural HDL

Checklist

Implementation Technology

Test 1 Review and sample problems

04-Oct Last Day to Change Majors before next Semester Enrollment

LABORATORY 4: LPM Usage in Structural HDL

Checklist

Week 8

9-Oct

Fall Break

NO CLASS

Implementation Technology

11-Oct

FPGA Architecture

Week 9

16-Oct

LABORATORY 4 (Extended): LPM Usage in Structural HDL

Checklist

FPGA Architecture

18-Oct

LABORATORY 4 (Extended): LPM Usage in Structural HDL

Checklist

FPGA Architecture

Test 1

Week 10

23-Oct

LABORATORY 5: Design Timing Analysis

Checklist

Notes

Timing in Digital Systems

25-Oct

LABORATORY 5: Design Timing Analysis

Checklist

Notes

Timing in Digital Systems

Week 11

30-Oct

LABORATORY 6: Bit-level Pipelining

Checklist

Reading Assignment Chapter 2: (Reese/Thornton)

FPGA Timing and Data Sheets and Device Packaging

01-Nov

Friday Nov 4: Last Day to Drop a Course

LABORATORY 6: Bit-level Pipelining

Checklist

Reading Assignment Chapter 2: (Reese/Thornton)

Bit-Level Pipelining

Week 12

06-Nov

NO LAB THIS WEEK

FSMD Design

Algorithmic State Machine Charts

Test 2 Review

08-Nov

NO LAB THIS WEEK

Test 2

Week 13

13-Nov

LABORATORY 7: Controller Specification and Synthesis Using HDLs

Checklist

Controller Specification using HDL

15-Nov

LABORATORY 7: Controller Specification and Synthesis Using HDLs

Checklist

Week 14

20-Nov

FINAL PROJECT: Matrix Multiplier

Cummings Paper on Blocking and Non-blocking Statements in Verilog

Resource Estimation and Scheduling

22-Nov

NO CLASS

Week 15

27-Nov

FINAL PROJECT: Matrix Multiplier

System Level Pipelining

Test 3 Review

29-Nov

Test 3

Week 16

04-Dec

Last day of instruction

State Assignment

06-Dec

FINAL PROJECT: Matrix Multiplier

Checklist

FINAL PROJECT

Thursday 07-Dec (11:30AM-2:30PM) JUNKINS 215

Last day to demonstrate the final project JUNKINS 215

FINAL PROJECT REPORT
Due on Canvas at: 11:59PM

SMU Final Exam Schedule

FINAL PROJECT REPORT
Due on Canvas at: 11:59PM

Grading Policy

Grade
Laboratory Exercises 40%
Test 1 (in-class) 15%
Test 2 (in-class) 15%
Test 3 (in-class) 15%
Final Project Report 15%

Note: Grades on labs/tests/final will range from 0-100.
However, the final class grade will be scaled to fit the above grading policy.
(1 lab point is not equal to 1 test point)

Lab Policy

Lab report format

Grading Policy Acknowledgement Form

Late Assignments

Unless a documented and legitimate reason is provided, all labs turned in late will automatically have 20% of the total possible points deducted for each lab period that has elapsed since the due date. As an example, a 100-point lab that was due on Wednesday but turned in on Thursday will be graded as normal and then 20 additional points will be deducted for being late.

All labs are due at the beginning of the lab period

Students who do not turn in labs or participate in the laboratory will not pass this class. You must attend and turn-in at least 80% of all laboratories to avoid receiving a failing grade.

Makeup Examinations

There will be no makeup examinations, a missed examination will result in 0% unless a valid and documented excuse is presented. If possible, students should provide such documentation before the examination date. In any event, notification must be provided within 2 class periods following the missed examination. In the case of a legitimate excuse for missing an examination, an alternative for making up this portion of total grade will be provided to the student.

Information

Disability Accommodations:

Students needing academic accommodations for a disability must first register with Disability Accommodations & Success Strategies (DASS). Students can call 214-768-1470 or visit http://www.smu.edu/Provost/ALEC/DASS to begin the process. Once registered, students should then schedule an appointment with the professor as early in the semester as possible, present a DASS Accommodation Letter, and make appropriate arrangements. Please note that accommodations are not retroactive and require advance notice to implement.

Religious observance

Religiously observant students wishing to be absent on holidays that require missing class should notify their professors in writing at the beginning of the semester, and should discuss with them, in advance, acceptable ways of making up any work missed because of the absence. (See University Policy No. 1.9.)

Excused absences for university extracurricular activities

Students participating in an officially sanctioned, scheduled University extracurricular activity should be given the opportunity to make up class assignments or other graded assignments missed as a result of their participation. It is the responsibility of the student to make arrangements with the instructor prior to any missed scheduled examination or other missed assignment for making up the work. (University Undergraduate Catalogue)