Research Objective

  • Mixed-Signal(Analog/Digital) Integrated Circuits and Systems Design
  • High Performance Mixed-Signal/Analog IC for High-Speed Wireless Communication
  • RF/Microwave IC Design for Sensing/Imaging and Biomedical Applications
  • Energy-Efficient Memory and Multi-Core Microprocessor Architecture

Key News

  • Dr. Byun received the prestigious NSF CAREER Award, NSF FRS and NSF BRIGE Awards
  • Dr. Byun directed NSF-CAREER, NSF-FRS, NSF-BRIGE, NSF-REU, SRC and other key projects.

Award & Honor

  • NSF CAREER Award, sole-PI (2014)
  • NSF FRS Award, sole-PI, one of 15 awardees nationwide (2013)
  • NSF BRIGE Award, sole-PI, one of 25 awardees nationwide (2012)
  • Outstanding Researcher of the Year (2014)
  • Senate Research Award (2012)
  • Study Abroad Scholarship, Korea Science and Research Foundation (2005)

Key Representative Paper

  • M. Jalalifar and G. Byun, "A 14.4Gb/s/pin 230fJ/b/pin/mm Multi-Level RF-Interconnect for Global Network-on-Chip Communication," IEEE Asian Solid-State Circuits Conference (ASSCC), pp.1-4, Nov, 2016. (Accepted)

  • H. Wang, C. Park, G. Byun, J. Ahn and N. Kim "Parallel-Serial Memory Channel Architecture for Single-Chip Heterogeneous Processor Systems," IEEE/ACM Int. Symp. on High-Performance Computer Architecture (HPCA) pp. 1-11, Feb. 2015. (AR: 22%)

  • Y. Kim, G. Byun, et al., "An 8Gb/s/pin 4pJ/b/pin Single-T-Line Dual (Base+RF) Band Simulataneous Bidirectional Mobile Memory I/O Interface with Inter-Channel Interference Suppression," IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp.50-51, Feb. 2012. (AR: 15%)

  • G. Byun, et al., "An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling," IEEE Journal of Solid-State Circuits (JSSC), vol 47, no 1, pp. 117-130, Jan. 2012.

  • G. Byun, et al., "An 8.4Gb/s 2.5pJ/b Mobile Memory I/O Interface Using Bi-directional and Simultaneous Dual (Base+RF)-Band Signaling," IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 488-489, Feb. 2011. (AR: 15%)

  • K. Kim, Y. Sohn, C. Kim, G. Byun, et al., "A 20GB/s 256MB DRAM with an Inductorless Quadrature PLL and a Cascaded Pre-emphasis Transmitter," IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 470-471, Feb. 2005. (AR: 15%)

  • K. Kim, J. Lee, W. Lee, B. Jeong, G. Cho, J. Lee, G. Byun, et. al, "1.4 Gbps DLL Using 2nd Order Charge Pumping Scheme for Low Phase/Duty Error for High Speed DRAM Application," IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 212-213, Feb. 2004. (AR: 15%)

  • H. Song, J. Kwak, G. Byun, et. al., "A 1.2Gb/s /pin Double Data Rate SDRAM with On-Die-Termination," IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp.1-10, Feb. 2003. (AR: 15%)

  • C. Yoo, G. Han, N. Heo, G. Byun, et. al., "A 1.8V 700Mb/s/Pin 512Mb DDR-II SDRAM with On-Die Termination and Off-Chip Driver Calibration," IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 1-15, Feb. 2003. (AR: 15%)

Journal Paper

  • [J25] N. Mirzaie and G. Byun, "3D Pipeline ADC Including TSV and Design Optimization," 2017 (SCI, Under Review)

  • [J24] M. Jalalifar and G. Byun, "An Energy-Efficient Multi-level RF-Interconnect for Global Network-on-Chip Communication," 2017 (SCI, Under Review)

  • [J23] A. Alzahmi, N. Mirzaie and G. Byun, "Performance-Aware 3D Power Delivery Network Using Optimal Regulator Placement," IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), Aug. 2017, Accepted (SCI)

  • [J22] M. Jalalifar and G. Byun, "A Wide-Range Low-Power PLL-Based PI Multiphase Generator Using Adaptive Frequency Tracking Technique," IEEE Transactions on Circuits and Systems II (TCAS-II), vol. 64, pp.1-5, Jul. 2017, Accepted (SCI)

  • [J21] M. Jalalifar and G. Byun, "A Low-Power Low-Jitter DLL with a Differential Closed-Loop Duty Cycle Corrector," Analog Integrated Circuits and Signal Processing (AICSP), vol. 90, pp.1-8, 2017 (SCI)

  • [J20] N. Mirzaie, H. Shamsi and G. Byun, "Yield-Aware Sizing of Pipeline ADC Using a Multi-Objective Evolutionary Algorithm," International Journal of Circuit Theory and Applications (IJCTA), vol. 47, pp. 1-8, 2017 (SCI)

  • [J19] N. Mirzaie, H. Shamsi and G. Byun, "Resilient Design of Current Steering DACs Using a Transistor Level Approach," Analog Integrated Circuits and Signal Processing (AICSP), vol. 90, pp. 29-41, 2017 (SCI)

  • [J18] N. Mirzaie, H. Shamsi and G. Byun, "Automatic design and yield enhancement of data converters," Journal of Circuits, Systems, and Computers, vol. 26, no. 1, pp. 1-19, 2017 (SCIe)

  • [J17] M. Jalalifar and G. Byun, "A Near-Threshold Energy-Efficient ASK Transmitter for Biomedical Implants," IEEE Canadian Journal of Electrical and Computer Engineering, vol. 39, no. 4, pp. 292-296, Dec. 2016

  • [J16] M. Jalalifar and G. Byun, "An Energy-Efficient Mobile Memory I/O Interface Using Simultaneous Bidirectional Multilevel Dual-Band Signaling ," IEEE Transactions on Circuits and Systems II (TCAS-II), vol. 63, pp.1-5, Oct. 2016 (SCI)

  • [J15] M. Jalalifar and G. Byun, "A Current-Reused QVCO Using Transformer Feedback Structure," IEEE Microwave and Wireless Components Letters (MWCL), vol. 26, no. 7 pp. 534-536, Jul. 2016 (SCI)

  • [J14] M. Jalalifar and G. Byun, "A Wide Range CMOS Temperature Sensor with Process Variation Compensation for On-Chip Monitoring," IEEE Sensors Journal (SJ), vol. 16, no. 14 pp. 5536-5542, Jul, 2016 (SCIe)

  • [J13] M. Jalalifar and G. Byun, "Design of a Varactor-Based Coupling QVCO Using Bulk-Injection Technique," Analog Integrated Circuits and Signal Processing (AICSP), vol. 86, no. 2, pp.227-232, Jan. 2016. (SCI)

  • [J12] M. Jalalifar and G. Byun, "Design of a Ku-Band Transformer-Based Cross-Coupled Complementary LC-VCO," IET Electronics Letters (EL), vol. 51, no. 11, pp.832-834, May 2015. (SCI)

  • [J11] G. Byun and M. Navidi "A Low-Power 4-PAM transceiver using a Dual-Sampling Technique for Heterogeneous Latency Sensitive Network-on-Chip," IEEE Transactions on Circuits and Systems II (TCAS-II) vol. 62, no. 6, pp. 613-617, Jun. 2015 (SCI)

  • [J10] M. Jalalifar and G. Byun, "A K-Band Divide-by-Five Injection-Locked Frequency Divider Using a Near-Threshold VCO," IEEE Microwave and Wireless Components Letters (MWCL) vol. 24, no. 12, pp. 881-883, Dec. 2014. (SCI)

  • [J9] M. Jalalifar and G. Byun, "An Ultra-Low Power QVCO Using Current- Coupling and Bulk-Injection Techniques," IEEE Microwave and Wireless Components Letters (MWCL) vol. 24, no. 11, pp. 781-783, Nov. 2014. (SCI)

  • [J8] M. Jalalifar and G. Byun, "An Ultra-Low Power Quadrature VCO for 2.4GHz-Band IEEE 802.15.4 Standard," IET Electronics Letters (EL), vol. 50, no. 16, pp.1168-1169, Jul. 2014. (SCI)

  • [J7] M. Jalalifar and G. Byun, "A Near-Threshold Charge Pump Circuit using a Dual Feedback Loop," IET Electronics Letters (EL), vol. 49, no. 23, pp. 1436-1438, Nov. 2013. (SCI)

  • [J6] Kanit T., G. Byun, J. Ir, G. Reinman, J. Cong and F. Chang, "Utilizing Radio Frequency Interconnect for a Many-DIMM DRAM System," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol 2, no 2, pp. 210-227, Jun. 2012. (SCIe)

  • [J5] Y. Kim, S. Tam, G. Byun, H. Wu, L. Nan, G. Reinman, J. Cong and F. Chang, "Analysis of Non-Coherent ASK Modulation Based RF-Interconnect for Memory Interface," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol 2, no 2, pp. 200-209, Jun. 2012. (SCIe)

  • [J4] I. Seok, H. Kim and G. Byun, "Structural Optimization of a Thin Film Solar Cell using Numerical Simulation and Design of Experiment Techniques," Journal of Material Science and Technology (JMST), vol 29, no 6, pp. 2557-2563, 2012. (SCIe)

  • [J3] Kanit T., G. Byun, J. Cong, F. Chang, and G. Reinman, "Utilizing RF-I and Intelligent Scheduling for Better Throughput/Watt in a Mobile GPU Memory System," ACM Transactions on Architecture and Code Optimization (TACO), vol 8, no. 4, pp. 1-19, Jan. 2012. (SCIe)

  • [J2] G. Byun, Y. Kim, J. Kim, R. Tam and F. Chang, "An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling," IEEE Journal of Solid-State Circuits (JSSC), vol 47, no 1, pp. 117-130, Jan. 2012. (Invited) (SCI)

  • [J1] J. Kim, G. Byun, and F. Chang, "A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and-Off-Chip Interconnects," IEICE Transactions on Electronics, vol. E94-C, no. 5, May 2011. (SCIe)

Conference Paper

  • [C24] M. Jalalifar and G. Byun, "A 14.4Gb/s/pin 230fJ/b/pin/mm Multi-Level RF-Interconnect for Global Network-on-Chip Communication," IEEE Asian Solid-State Circuits Conference (ASSCC), pp.1-4, Nov, 2016. (Accepted)

  • [C23] G. Byun, "High-speed 3D CMOS Interconnect for Mobile DRAMs," IEEE International SOC Design Conference (ISOCC), Oct. 2016. (Accepted)

  • [C22] G. Byun "Energy-efficient 3D Mobile Memory Interface for Mobile Computing Devices ," IEEE US-Korea Conference on Science, Technology, and Entrepreneurship (UKC), Aug. 2016.

  • [C21] G. Byun "Energy-efficient Clock Distribution Network for 3D-stacked Mobile Devices," IEEE Collaborative Conference on 3D & Materials Research (CC3DMR), Jun. 2016.

  • [C20] H. Wang, C. Park, G. Byun, J. Ahn and N. Kim "Parallel-Serial Memory Channel Architecture for Single-Chip Heterogeneous Processor Systems," IEEE/ACM Int. Symp. on High-Performance Computer Architecture (HPCA) pp. 1-11, Feb. 2015. (AR: 22%)

  • [C19] M. Jalalifar and G. Byun, "A Dual Positive Feedback Three-Stage Low Noise Amplifier," IEEE Dallas Circuits and Systems Conference (DCAS), pp. 1-5, Oct. 2014. (AR: TBD)

  • [C18] M. Jalalifar and G. Byun, "An Energy-Efficient Mobile PAM Memory Interface for Future 3D Stacked Mobile DRAMs," IEEE 15th International Symposium on Quality Electronic Design (ISQED), pp. 1-5, Mar. 2014. (AR: 30%)

  • [C17] M. Navidi and G. Byun, "Comparative Analysis of Clock Distribution Networks for TSV-based 3D IC Designs," IEEE 15th International Symposium on Quality Electronic Design (ISQED), pp. 1-5, Mar. 2014. (AR: 30%)

  • [C16] M. Jalalifar and G. Byun, "An Ultra-Low-Power Spike Detector for Implantable Biomedical Systems," IEEE 14th Wireless and Microwave Technology Conference (WAMICON), pp. 1-4, Apr. 2013.

  • [C15] M. Navidi and G. Byun, "An ASK Demodulator for Ultra-Low-Power Implantable Biomedical Microsystems," IEEE 14th Wireless and Microwave Technology Conference (WAMICON), pp. 1-4, Apr. 2013.

  • [C14] A. Dilello and G. Byun, "An Ultra-Low-Power ASK Modulator for Back Telemetry Applications," IEEE 14th Wireless and Microwave Technology Conference (WAMICON), pp. 1-4, Apr. 2013.

  • [C13] D. Chang, G. Byun, N. Kim, M. Schulte, "Reevaluating the Latency Claims of 3D Stacked Memories," Proceedings of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-6, Jan. 2013. (AR: 30%)

  • [C12] Y. Kim, G. Byun, A Tang, J. Cong, G. Reinman and F. Chang, "An 8Gb/s/pin 4pJ/b/pin Single-T-Line Dual (Base+RF) Band Simulataneous Bidirectional Mobile Memory I/O Interface with Inter-Channel Interference Suppression," IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 50-51, Feb. 2012. (AR: 15%)

  • [C11] Kanit T., G. Byun*, J. Cong, F. Chang, and G. Reinman, "Intelligent Scheduling Mobile RF-I for Better Throughput/Watt in a Mobile GPU Memory System," Proceedings of the 7th International Conference on High-Performance and Embedded Architectures and Compliers (HiPEAC), Paris, France, Jan. 2012. (*presenter, AR=25%)

  • [C10] R. Tam, F. Chang, J. Kim, G. Byun, "Wireline/Wireless RF-Interconnect for Future SoC," IEEE International Symposium on RF Integration Technology, pp. 44-48, Dec. 2011. (Invited)

  • [C9] Kanit T., G. Byun, J. Ir, G. Reinman, J. Cong and F. Chang, "The DIMM Tree Architecture: A High Bandwidth and Scalable Memory System," IEEE International Conference on Computer Design (ICCD), pp. 388-395, Oct. 2011. (AR: 32%)

  • [C8] J. Kim, G. Byun, and F. Chang, "RF Interconnect Technology for On-chip and Off-chip Communication," Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), IEICE ED2010-75, pp. 105-108, 2011.

  • [C7] G. Byun, Y. Kim, J. Kim, R. Tam, J. Cong, G. Reinman, and F. Chang, "An 8.4Gb/s 2.5pJ/b Mobile Memory I/O Interface Using Bi-directional and Simultaneous Dual (Base+RF)-Band Signaling," IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 488-489, Feb. 2011. (AR: 15%)

  • [C6] J. Choi, Y. Sohn, C. Kim, W. Park, J. Lee, U. Kang, G. Byun, I. Park, B. Kim, H. Hwang, C. Kim and S. Cho, "A 5.0Gbps/Pin Packet-Based DRAM with Low Latency Receiver and Process Insensitive PLL," IEEE Symposium on VLSI Circuits (VLSI) Digest Technical Papers, pp. 50-51, Jun. 2005. (AR: 25%)

  • [C5] K. Kim, Y. Sohn, C. Kim, G. Byun, H. Lee, J. Lee, J. Sunwoo, J. Choi, J. Chai, C. Kim and S. Cho, "A 20GB/s 256MB DRAM with an Inductorless Quadrature PLL and a Cascaded Pre-emphasis Transmitter," IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 470-471, Feb. 2005. (AR: 15%)

  • [C4] Y. Sohn, J. Choi, I. Chung, C. Kim, G. Byun, D. Kang, W. Park, I. Park, H. Hwang, C. Kim and S. Cho, "A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme," IEEE Symposium on VLSI Circuits (VLSI) Digest Technical Papers, pp. 36-37, Jun. 2004. (AR: 25%)

  • [C3] K. Kim, J. Lee, W. Lee, B. Jeong, G. Cho, J. Lee, G. Byun, C. Kim, Y. Jun and S. Cho, "1.4 Gbps DLL Using 2nd Order Charge Pumping Scheme for Low Phase/Duty Error for High Speed DRAM Application," IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 212-213, Feb. 2004. (AR: 15%)

  • [C2] H. Song, J. Kwak, G. Byun, W. Lee, Y. Jun and S. Cho, "A 1.2Gb/s /pin Double Data Rate SDRAM with On-Die-Termination," IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp.1-10, Feb. 2003. (AR: 15%)

  • [C1] C. Yoo, G. Han, N. Heo, G. Byun, D. Lee, H. Choi, H. Kim, C. Kim, and S. Cho, "A 1.8V 700Mb/s/Pin 512Mb DDR-II SDRAM with On-Die Termination and Off-Chip Driver Calibration," IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 1-15, Feb. 2003. (AR: 15%)

Patents

  • [P14] F. Chang, S. Tam, G. Byun, et. al, "Multi-band interconnect for inter-chip and intra-chip communications" US9178725, 2015

  • [P13] G. Byun, M. Park and H. Kim "Semiconductor memory devices including a built-in self-test (BIST) circuit," US patent 2007/0047347, 2009

  • [P12] G. Byun, K. Kim and W. Kim, "Semiconductor driver circuit with signal swing balance and enhanced testing," US7598762, 2009

  • [P11] G. Byun, "Semiconductor device including duty cycle correction (DCC) circuit," US7292499, 2007

  • [P10] G. Byun and I. Bae, "Differential output driver with advanced on-die-termination (ODT)," US7288967, 2006

  • [P9] G. Byun and J. Choi, "Layout structure of signal driver," US7274259, Sep. 2007

  • [P8] G. Byun, "Delay-locked-loop (DLL) capable of performing reliable locking operation," US7190200, Mar. 2007

  • [P7] G. Byun, "Semiconductor device having DLL and test method thereof," US7123540, Oct. 2006

  • [P6] G. Byun and N. Heo, "DLL capable of compensating for delay of internal clock signal by variation of driving strength of output driver in semiconductor memory device," US7068084, Jun. 2006

  • [P5] G. Byun, "Semiconductor device having DLL and bias generator by MRS," Korea Patent No. 0046921, 2003

  • [P4] G. Byun, "Auto-detecting DCC immune to process variation," Korea Patent 0510515, 2003

  • [P3] G. Byun, "Novel clock buffer changing feedback path and real data path," Korea Patent No. 0097487, 2002

  • [P2] G. Byun and J. Kim, "Programmable bias current generator," Korea Patent No. 0088558, 2002

  • [P1] G. Byun, "DLL capable of calibrating phase detector of the best linearity," Korea Patent No. 0015617, 2001