#
# Design  : risc_design
# Library : Synopsys Library Services, Odyssey Demo Library
#
# T. Manikas modification for GWU labs  12-5-11
#



#
##
##
set cache_read ""
set cache_write ""
 
##
##

# Search Path
set search_path "$search_path ./report ./src ./db ./"

# Setup libraries
set link_library  "osu05_stdcells.db"
set target_library "osu05_stdcells.db"
set symbol_library "generic.sdb"
set synthetic_library [list dw_foundation.sldb]

# Define Work Library Location
define_design_lib WORK -path "./work"

#/* ================================================= */ 
#/* General configuration settings. */ 
#/* ================================================= */ 

# Warn if latches are inferred 
set hdlin_check_no_latch true 

# Treat text between translate statements as comments 
set hdlin_translate_off_skip_text true 

# 
set verilogout_write_components true 

# Determines the name that will be used for the architecture of the write -f verilog command 
set verilogout_architecture_name "structural" 

# Turn tri state nets from "tri" to "wire" 
set verilogout_no_tri true 

# Treat text between translate statements as comments 
set hdlin_translate_off_skip_text true 

# List of package commands 
set vhdlout_use_packages [list IEEE.std_logic_1164.ALL] 

# Write out component declarations for cells mapped to a technology library. 
set vhdlout_write_components true
# Determines the name that will be used for the architecture of the write -f vhdl command 
set vhdlout_architecture_name "structural" 

# Treat text between translate statements as comments 
set hdlin_translate_off_skip_text true 

# Specify the styel to use in naming an individual port member 
set bus_naming_style {%s[%d]}