// fulladder_tb.v		T. Manikas	2-24-19
// testbench to test fulladder.v


module test_FA;
	reg a,b,cin;
	wire s,cout;
	full_adder u1(s,cout,a,b,cin);
	initial
	begin
		cin = 1'b0;
		a = 1'b0;
		b = 1'b0;
	end
	initial
	begin
		#50 b = 1'b1;
		#50 a = 1'b1;
		#50 cin = 1'b1;
		#50 b = 1'b0;
		#50 a = 1'b0;
	end
	initial $monitor($time, " a=%b b=%b cin=%b s=%b, cout=%b",
				a,b,cin,s,cout);
	initial #300 $stop;
endmodule