ECE 5387/7387 Digital Systems Design - Class Schedule
ECE 5/7387 Digital Systems Design - Class Schedule

WEEK

DATE

EVENTS/HOLIDAYS

OTHER CLASS NOTES
AND LABORATORY

CLASS TOPIC
AND OVERHEADS

Week 1

26-Aug

 

First Day of Class
 

Class Introduction

 
28-Aug
 
Reading Assignment Chapter 1
(Reese/Thornton)

Week 2

02-Sep

NO CLASS SMU HOLIDAY

NO LAB THIS WEEK 

NO CLASS SMU HOLIDAY

 
04-Sep
 

NO LAB THIS WEEK

Week 3

09-Sep

 

LABORATORY 0

 

Sequential Logic Review - Part 1

 
11-Sep
Last Day to Request Excused Absence for Observance of a Religious Holiday
 

Week 4

16-Sep

 

LABORATORY 1

Sequential Logic Review - Part 2

 
18-Sep
   

Lab Procedures
AND
CMOS Logic/Process Review

Week 5

23-Sep

 

LABORATORY 1

Event Driven Simulation

Verilog Introduction for Combinational Logic - Part 1

 

25-Sep

   

Verilog Introduction for Combinational Logic - Part 1

Week 6

30-Sep

 

LABORATORY 2

testbench file


Verilog Introduction for Combinational Logic - Part 2

 

02-Oct

 



 

 

Vivado Constraint Files

Week 7

07-Oct

 

LABORATORY 3
testbench file

Verilog Introduction for Combinational Logic - Part 2

Test 1 Review

 
09-Oct
Last Day to Change Majors before next Semester Enrollment  
Test 1

Week 8

14-Oct

Fall Break

NO CLASS

NO LAB THIS WEEK

 

Verilog Introduction for Combinational Logic - Part 2

 

16-Oct

Last day for continuing undergraduates to change major before November enrollment

 

Verilog Introduction for Combinational Logic - Part 2

Week 9

21-Oct

 

LABORATORY 4

Verilog Introduction for Combinational Logic - Part 2

Timing in Digital Systems

 

23-Oct

 

 

Timing in Digital Systems

Week 10

28-Oct

 

LABORATORY 5

 

Timing in Digital Systems

 

30-Oct

 

 

Timing Analyzers

Algorithmic State Machine Charts

Week 11

04-Nov

 

LABORATORY 6

c17.v

 

Reading Assignment Chapter 2
(Reese/Thornton)

 

FSMD Design

 

06-Nov

FRIDAY NOV. 8: Last Day to Drop a Course

FPGA Timing and Data Sheets and Device Packaging

Controller Specification using HDL

 

Week 12

11-Nov

 

LABORATORY 7

Controller Specification using HDL

 

13-Nov

 

State Assignment

Bit-Level Pipelining

Week 13

18-Nov

 

Cummings Paper on Blocking and Non-blocking Statements in Verilog

Bit-Level Pipelining

 

 
20-Nov
 

Implementation
Technology

FPGA Architecture

Resource Estimation and Scheduling

Test 2 Review

Week 14

25-Nov

 

PROJECT

 

Test 2

 

 
27-Nov
NO CLASS
NO CLASS
NO CLASS

Week 15

02-Dec

 

PROJECT

Resource Estimation and Scheduling

System Level Pipelining

 

04-Dec

Dec. 4 - Dec. 9: No final exams or unscheduled tests and papers

 

System Level Pipelining

Week 16

09-Dec

 

Last Day of Class

PROJECT

System Level Pipelining


FINAL EXAM SCHEDULE

Thursday
12-Dec (11:30AM-2:30PM)

PROJECT DUE

(project demo files due to TA)
(Final Report due: 2:30PM)

PROJECT DUE

 

(project demo files due to TA)

(Final Report due: 2:30PM)