CSE  3381

Digital Logic Design

Homework No. 3

Due on: March 28.

  1. Derive the state diagram of the circuit shown in the following figure


  2. Design a sequential circuit using JK flip-flops for the state diagram shown in the figure. 

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  3. Design a serial 2's complement generator using JK Flipflops.

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  4.  Design a circuit which will detect a pattern 101 in the input bit stream. You may assume that the flipflops you use have asyncronous reset facility.