CSE 5381/7381
Computer Architecture
Spring 2000
Projects
Report Due May 5, 2000
As I have mentioned in the class, there are two projects: one
for the seniors in the class and the other for the graduate students.
Graduate Student Project - Simulation of Pipelined DLX Architecture
Design and build a simulator for the DLX instruction pipeline using the
verilog hardware description language or a language of your choce. It should
accept as input the memory map output of dlxas (the DLX assembler).
The simulator should work under the following modes:
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Without any pipelining.
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Basic DLX pipeline (as described in Chapter 3) without any optimizations
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(Optional for extra credit) Optimized DLX pipeline supporting Data Forwarding
The simulator does not need to handle floating point operations or interrupts.
A set of programs will be provided to test your simulation.
The final report should include a description of the instruction pipeline
design and the implementation. This should include details of what is done
at each stage of the pipeline as well as what information is flowing between
stages.
Timing results for the following cases should be included:
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Execution time of test codes with no pipelining.
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Execution time with pipelining.
Undergraduate Project - Cache Simulation
Write a cache simulator (in any language) that accepts memory addresses
and determines various statistics. The following caches should be simulated:
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Direct mapped
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4-way set associative cache
For each type of cache you are to simulate:
Finally, you should consider the following for the cache sizes:
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1Mbyte cache with blocksize of 32 bytes
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256Kbyte cache with blocksize of 8 bytes
With the above specifications, you are looking at 8 different combinations.
Assumptions
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LRU replacement strategy.
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Cache is initially empty.
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Cache is flushed at end of run.
Input Files
Your program should accept as input lines of the form
read/write address
where read/write is either R or W. address
is in the range 0 to 2^30. Sample inputs will be provided.
Statistics and Final Report
The following statistics need to be collected:
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Hit rate
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Bytes transferred from memory to the cache
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Bytes transferred from cache to memory
Your final report should include:
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Description of program design
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Table of results for all runs
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Copy of source code, transcript of simulation runs