CSE 5381/7381

Computer Architecture

Spring 2000

Projects

Report Due May 5, 2000

As I have mentioned in the class, there are two projects: one for the seniors in the class and the other for the graduate students.

Graduate Student Project - Simulation of Pipelined DLX Architecture

Design and build a simulator for the DLX instruction pipeline using the verilog hardware description language or a language of your choce. It should accept as input the memory map output of dlxas (the DLX assembler). The simulator should work under the following modes:

Without any pipelining.
Basic DLX pipeline (as described in Chapter 3) without any optimizations
(Optional for extra credit) Optimized DLX pipeline supporting Data Forwarding

The simulator does not need to handle floating point operations or interrupts. A set of programs will be provided to test your simulation.

The final report should include a description of the instruction pipeline design and the implementation. This should include details of what is done at each stage of the pipeline as well as what information is flowing between stages.

Timing results for the following cases should be included:

Execution time of test codes with no pipelining.
Execution time with pipelining.

Undergraduate Project - Cache Simulation

Write a cache simulator (in any language) that accepts memory addresses and determines various statistics. The following caches should be simulated:

Direct mapped
4-way set associative cache

For each type of cache you are to simulate:

Write-back
Write-through

Finally, you should consider the following for the cache sizes:

1Mbyte cache with blocksize of 32 bytes
256Kbyte cache with blocksize of 8 bytes

With the above specifications, you are looking at 8 different combinations.

Assumptions

LRU replacement strategy.
Cache is initially empty.
Cache is flushed at end of run.

Input Files

Your program should accept as input lines of the form

read/write address

where read/write is either R or W. address is in the range 0 to 2^30. Sample inputs will be provided.

Statistics and Final Report

The following statistics need to be collected:

Hit rate
Bytes transferred from memory to the cache
Bytes transferred from cache to memory

Your final report should include:

Description of program design
Table of results for all runs
Copy of source code, transcript of simulation runs