Verilog - Cadence SimVision

Verilog is a hardware description language (HDL) for developing and modeling circuits. The Cadence SimVision tool will help you simulate circuits that have been developed in Verilog. A useful tutorial to get started is the following: To use the tool, start up your X-Windows emulator to get an X-terminal window. At the X-terminal window, you may create Verilog files and run the Verilog program as directed in the document.

Verilog Language Help

SMU Resources

There is an e-book available to SMU students from the SMU library site: http://smu.edu/libraries/.

Do a "Quick Search" on the "Library Catalog" title "Design through Verilog HDL". This will get you the e-book by T.R. Padmanabhan, which is an introductory text on Verilog. Click on the "Linked Resources" link at the bottom.

Note: if you are connecting to the library site from off-campus, you will need to enter information from your SMU ID card for authentication before you will be allowed access to the e-book.

Web Resources

If you are looking for short tutorials on the basics of Verilog, the following web links may be helpful:

Developing Verilog Testbenches

After you have developed your Verilog system modules, you will need to develop "testbench" modules to test your system modules. A useful tutorial for developing Verilog testbenches is the following:
T. Manikas Last update 2014 Jul 3