CSE 3381 Digital Logic Design

WEEK

DATE

EVENTS/HOLIDAYS

READING, HOMEWORK, AND LAB EXPERIMENTS

CLASS TOPIC AND OVERHEADS

Week 1

22-Aug

First Day of Class NO LAB THIS WEEK

 

Appendix B: Number Systems, pp. 334-346

NO CLASS MEETING

 

24-Aug

26-AUG: Last day to enroll, add, drop with no record

Homework 1

Class Introduction

Number Systems

Week 2

29-Aug

 

NO LAB THIS WEEK

Chapter 1: pp. 1-8

Signed Numbers

 

31-Aug

 

 

Signed Numbers

Week 3

05-Sep

NO CLASS

University Holiday

NO LAB THIS WEEK

Chapter 2: pp. 9-25


NO CLASS

 

07-Sep

Last day to request excused absence for observance of a religious holiday

Laboaratory Discussion and Software Installation

Homework 2.1, 2.2, 2.3, 2.5, 2.7, 2.8, 2.11

Signed Numbers

Week 4

12-Sep

 

HOMEWORK DUE

LAB EXPERIMENT 1
(Example 1, Lab Manual, p. 6-10)

Chapter 3: pp. 28-49

Signed Numbers

Logic Gates

 

14-Sep

 

Chapter 4: pp. 52-55

 

CMOS Logic Gate Circuits

Gates and Transistors

Week 5

19-Sep

 

LAB EXPERIMENT 2
(Textbook, pp. 26-27, problems 2.12, 2.13, 2.14, 2.15)


 

21-Sep

 

Canonic Forms

Week 6

26-Sep

27 Sep: Early Intervention Grades Reported

LAB EXPERIMENT 3
(Textbook, Example 3 p. 45:Majority Circuit; Example 4 p. 47: 2-bit Comparator; Problem 3.8 p. 51)

 

HOMEWORK DUE

Homework 3.1, 3.2, 3.4, 3.5, 3.7, 3.8

Logic Gates and Minimization

 

28-Sep

 

Logic Gates and Minimization

 

Week 7

03-Oct

 

LAB EXPERIMENT 4
(from Lab Manual NOT the thicker textbook:
Problem 3.2, p. 19, 2x4 Decoder, Example 4, p. 20, Equality Detector, Example 5, p. 22, 2:1 Multiplexer)

 

 

 

 

Logic Gates and Minimization

EXAM 1 REVIEW

 

05-Oct

Last Day to Change Majors before next Semester Enrollment

HOMEWORK DUE

EXAM 1

Week 8

10-Oct

NO CLASS

Holiday - Fall Break - Oct 10 & 11

NO CLASS

NO LAB THIS WEEK

NO CLASS

 

 

12-Oct

 

Chapter 4: pp. 55-63

 

Homework 4.1, 4.2, 4.3, 4.4

Logic Gates and Minimization

Week 9

17-Oct

 

LAB EXPERIMENT 5
(from Lab Manual NOT the thicker textbook:
Example 6 Quad 2-1 Multiplexer, p. 25, Example 7 4-1 Multiplexer, p. 30 and Example 9-7 Segment Decoder, p. 42)

 

 

Programmable Logic

 

 

19-Oct

Oct 23: Mid-Term Grades Reported for First and Second Year Students

HOMEWORK DUE

 

Chapter 5: pp. 64-116

Homework 5.1, 5.13, 5.16, 5.23, 5.25

 

Verilog Introduction-Modules and Primitives

Combinational Building Blocks

Week 10

24-Oct

 

 

LAB EXPERIMENT 6

Student ID Project

Chapter 6: pp. 120 - 150

Combinational Building Blocks

 

26-Oct

 

 

Building Blocks and Transistors

 

Arithmetic Circuits

Week 11

31-Oct

 

 

LAB EXPERIMENT 7

MUX & Arithmetic Project

Chapter 7: pp. 151 - 184 

HOMEWORK DUE

 

Homework 6.4, 6.8, 6.9 (arithmetic circuits)

Arithmetic Circuits

 

02-Nov

Friday Nov. 4: Last day to drop a course

 

Arithmetic Circuits

Week 12

07-Nov

 

LAB EXPERIMENT 8

CLA Adder Circuit

HOMEWORK DUE

 

Homework 7.2, 7.3, 7.5, 7.6, 7.17 (you do not have to write the Verilog program for 7.17, just draw the K-maps and logic diagrams instead)

 

 

Arithmetic Circuits

Latches, Flip-flops and Characteristic

 

 

09-Nov

 

 

Latches, Flip-flops and Characteristic

EXAM 2 Review

Week 13

14-Nov

 

LAB EXPERIMENT 9 

Pseudo-Random Number Generator
(Linear Feedback Shift Register)

READING: Chapter 8: pp. 206 - 223

EXAM 2

Latches, Flip-flops and Characteristic

 

16-Nov

 

HOMEWORK DUE

HOMEWORK: 8.2, 8.3, 8.4, 8.5

Synchronous Sequential Circuit Design

Week 14

21-Nov

 

NO LAB THIS WEEK

 

 

 

FSM Models and Verilog Descriptions

 

23-Nov

NO CLASS DAY

NO CLASS

NO CLASS

Week 15

28-Nov

 

LAB EXPERIMENT 10

Finite State Machine Synthesis

Chapter 9: pp. 225 - 246

Controllers and Datapaths

 

30-Nov

Nov. 30 - Dec. 5 : No final exams or unscheduled tests and papers

HOMEWORK DUE

Controllers and Datapaths

Exam 3 Review
Week 16
05-Dec
Last Day of Instruction   EXAM 3
FINAL EXAM SCHEDULE Tuesday 13-Dec (3-6 PM)

Final Project Report Due (3:00PM)

NEW!!! INSTRUCTIONS

Final Project Report Due (3:00PM)

NEW!!! INSTRUCTIONS

Final Project Report Due (3:00PM)