JOURNAL ARTICLES

• General Process Detection Through Side Channel Characterization, Journal of Cyber Security Technology, 2024, (to appear, with M.A. Taylor, A. Sinha, E.C. Larson and M.A. Thornton).
  
• Automatic Modulation Classification with Deep Neural Networks, Electronics, 2023, 12, 3962, September 20, 2023, (with C.A. Harper and E.C. Larson).
• Silicon Photonics 2x2 Trench Coupler Design and Foundry Fabrication, Applied Optics, vol. 61, no. 16, June 2022, pp. 4927-4931, (with H. Shahoei, I.G. Achu, E.J. Stewart, U. Tariq, W.V. Oxford and D.L. MacFarlane).
• A 2.56 Gbps Serial Wireline Transceiver that Supports an Auxiliary Channel in 65 nm CMOS, IEEE Transactions on VLSI, vol. 28, iss. 1, pp. 12-22, January 2020, (pre-print version August 13, 2019, IEEEXplore.ieee.org, with X. Wang, T. Liu, S. Guo, and P. Gui).
• Higher Dimension Quantum Entanglement Generators, ACM Journal on Emerging Technologies in Computing Systems, vol. 16, no. 1, article 3, 21 pages, October 2019, ACM digital library, (with K.N. Smith).
• Consideration of Quality Attribute Tradeoffs of the Blockchain Pattern in the Software Development Process, Annals of Emerging Technologies in Computing, vol. 3, no. 4, October 2019, pp. 15 - 27, (with J.M. Medellin).
• Keyboard Snooping from Mobile Phone Arrays with Mixed Convolutional and Recurrent Neural Networks, Proc. of the ACM on Interactive, Mobile, Wearable and Ubiquitous Technologies, vol. 3, no. 2, June 2019, pp. 45-1 - 45-22, (with T. Giallanza, T. Siems, E. Sharp, E. Gabrielsen, I. Johnson, and E.C. Larson).
• Higher-radix Chrestenson Gates for Optical Quantum Computation, Journal of Applied Logics, vol. 5, iss. 9, pp. 1781-1798, December 2018, (with K.N. Smith, T.P. LaFave, Jr., and D.L. MacFarlane).
• A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number System, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, iss. 1, pp. 34-43, March 2016, (pre-print February 2016, IEEEXplore, with S.D. Gupta).
• QMDDs: Efficient Quantum Function Representation and Manipulation, IEEE Transactions on Computer-Aided Design, vol. 35, no. 1, pp. 86-99, January 2016, (pre-published July 21, 2015, IEEEXplore.ieee.org pre-print version, with P. Niemann, R. Wille, D.M. Miller, and R. Drechsler).
• Simulation and Implication using a Transfer Function Model for Switching Logic, IEEE Transactions on Computers, vol. 64, no. 12, pp. 3580-3590, December 2015, (pre-published February 6, 2015, IEEEXplore.ieee.org pre-print version).
• Quantum Multiple-Valued Decision Diagram: The Case of Skipped Variables, Journal of Multiple-Valued Logic and Soft Computing, vol. 24, 2015, no. 1-4, pp. 93-108, (with D.Y. Feinstein).
• Modeling System Threat Probabilities Using Mixed-Radix Multiple-Valued Logic Decision Diagrams, Journal of Multiple-Valued Logic and Soft Computing, vol. 24, 2015, no. 1-4, pp. 135-149, (with T. Manikas, and D.Y. Feinstein).
• On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems, IEICE Trans. Inf. & Syst., vol. E97-D, no. 9, September 2014, pp. 2234-2242, online library, (with S. Nagayama, T. Sasao, J.T. Butler, and T.W. Manikas).
• Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach, Journal of Multiple-Valued Logic and Soft Computing, vol. 22, no. 1-2, 2014, pp. 21-39, (with R.P. Menon).
• A Principles and Practices Exam Specification to Support Software Engineering Licensure in the United States of America, Software Quality Professional, December 2012, vol. 15, iss. 1, pp. 4-15, (with P.A. Laplante and B. Kalinowski).
• Professional Licensure for Software Engineers: An Update, IEEE Computing in Science and Engineering, IEEE Computer Society Press and American Institute of Physics, September-September/October 2012, no. 5, vol. 14, iss. 5, pp. 85-87, IEEEXplore.ieee.org version.
• Reversible Logic Synthesis Based on Decision Diagram Variable Ordering, Journal of Multiple-Valued Logic and Soft Computing, vol. 19, no. 4, 2012, pp. 325-339, (with D.Y. Feinstein).
• Business Process Development Through the Use of a Modified Axiomatic Design Methodology, Journal of International Business Management & Research, vol. 2, issue 4, May 2011, (with D. Easton).
• An Axiomatic Approach for Large-Scale Disaster-Tolerant Systems Modeling, IIIS Journal of Systematics, Cybernetics and Informatics, vol. 9, no. 1, 2011, pp. 89-93, (with T. Manikas, L.L. Spenner, P.D. Krier, S. Nair, and S.A. Szygenda).
• To PE or not to PE ... The Sequel, IEEE Computing in Science and Engineering, IEEE Computer Society Press and American Institute of Physics, July/August 2010, vol. 12, no. 4, pp. 62-65, (with Steven F. Barrett), IEEEXplore.ieee.org version.
• Minimization of Quantum Multiple-Valued Decision Diagrams using Data Structure Metrics, Journal of Multiple-Valued Logic and Soft Computing, vol. 15, no. 4, 2009, pp. 361-377, (with D.Y. Feinstein and D.M. Miller).
• Redundant Signed Binary Addition Based Digital-to-Frequency Converter, IEE Electronics Letters, vol. 45, no. 2, pp. 824-826, July 2009, (with W. Chen and P. Gui).
• A Discrete Logarithm Number System for Integer Arithmetic Modulo 2^k: Algorithms and Lookup Structures, IEEE Transactions on Computers, vol. 58, no. 2, Feb. 2009, pp. 163-174, (with A. Fit-Florea, L. Li, and D.W. Matula), IEEEXplore.ieee.org version.
• A Methodology for Disaster Tolerance Utilizing the Concepts of Axiomatic Design, IIIS Journal of Systemics, Cybernetics and Informatics, vol. 6, no. 4, 2008, (with D. Easton, V.S.S. Nair, and S.A. Szygenda).
• Components of Disaster Tolerant Computing: Analysis of Disaster Recovery, IT Application Downtime & Executve Visibility, International Journal of Business Information Systems,vol. 3, no. 3, 2008, pp. 317-331, (with C.M. Lawler, M.A. Harper, and S.A. Szygenda).
• QMDD Minimization using Sifting for Variable Reordering, Journal of Multiple-Valued Logic and Soft Computing, vol. 13, no. 4-6, 2007, pp. 537-552, (with D.M. Miller and D.Y. Feinstein).
• Integrated Design Validation: Combining Simulation and Formal Verification in Integrated Circuit Design, IIIS Journal of Systemics, Cybernetics and Informatics, vol. 4, no. 2, 2006, (with L. Li and S. Szygenda).
• A Coarse-Grain Phased Logic CPU, IEEE Transactions on Computers, vol. 54, no. 7, July 2005, pp. 788-799, (with R. B. Reese and C. Traver).
• Early Evaluation for Performance Enhancement in Phased Logic, IEEE Transactions on Computer Aided Design, (vol. 24, no. 4, pp. 532-550, April 2005, (with R. B. Reese, C. Traver, and D. Hemmendinger).
• Additive Bit-serial Algorithm for the Discrete Logarithm Modulo 2^k, IEE Electronics Letters, vol. 41, no. 2, pp. 57-59, January 2005, (with A. Fit-Florea and D.W. Matula).
• Addition-based Exponentiation Modulo 2^k, IEE Electronics Letters, vol. 41, no. 2, pp. 56-57, January 2005, ( with A. Fit-Florea and D.W. Matula).
• Computation of Discrete Function Chrestenson Spectrum Using Cayley Color Graphs, Journal of Multiple-Valued Logic and Soft Computing, vol. 10, no. 2, 2004, pp. 189-202, (with D. Michael Miller).
• Mixed-radix MVL Function Spectral and Decision Diagram Representation, Automation and Remote Control, vol. 65, issue 6, June 2004, pp. 1007-1017, (invited paper, in English and Russian).
• Two-phase Micropipeline Control Wrapper with Early Evaluation, IEE Electronics Letters, vol. 40, no. 6, March 2004, pp. 365-366, (with R. B. Reese and C. Traver).
• Fast Two-phase Micropipeline Control Wrapper for Standard Cell Implementation, IEE Electronics Letters, vol. 40, no. 4, February 2004, pp. 19-20, (with R. B. Reese and Cherrice Traver).
• Performance Evaluation of a Parallel Decoupled Data Driven Multiprocessor, Parallel Processing Letters, vol. 13, no. 3, September 2003, pp. 497-507.
• A Signed Binary Addition Circuit Based on an Alternative Class of Addition Tables, Computers & Electrical Engineering, vol. 29, no. 2, March 2003, pp. 303-315.
• Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation, Canadian Journal of Electrical and Computer Engineering, vol. 27, no. 4, October 2002, pp. 159-164, (invited paper, with R. Drechsler, M. Kerttu and P. Lindgren).
• Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs, VLSI Design, vol. 14, no. 1, February 2002, pp. 53-64, (with R. Drechsler and W. Günther).
• Boolean Function Representation and Spectral Characterization Using AND/OR Graphs, Integration, the VLSI Journal, vol. 29, September 2000, pp. 101-116, (with A. Žužek and R. Drechsler).
• Behavioral Synthesis of Combinational Logic Using Spectral Based Heuristics, ACM Transactions on Design Automation of Electronic Systems, vol. 4, no. 2, April 1999, pp. 219-230, ACM digital library, (with V. S. S. Nair).
• Resource Estimation for Parallel Architectures with Distributed Processor/Memory Nodes, Journal of Computing and Information Technology, vol. 6, no. 4, December 1998, pp. 359-371 (with D. L. Andrews).
• Signed Binary Addition Circuitry with Inherent Even Parity Outputs, IEEE Transactions on Computers, vol. 46, no. 7, July 1997, pp. 811-816.
• BDD Based Spectral Approach for Reed-Muller Circuit Realisation, IEE Proceedings-Computers and Digital Techniques, vol. 193, issue 2, March 1996, pp. 145-150, (with V. S. S. Nair).
• Efficient Calculation of Spectral Coefficients and Their Application, IEEE Transactions on Computer Aided Design, vol. 14, no. 11., November 1995, pp. 1328-1341, (with V. S. S. Nair).
• Efficient Calculation of Spectral Coefficients of Combinational Circuits, Digital Signal Processing, vol. 4, no. 4, October 1994, pp. 245-254, (with V. S. S. Nair).

BOOKS

• Modeling Digital Switching Circuits with Linear Algebra, Morgan & Claypool Publishers, San Rafael, California, ISBN 9781627052337 (hardcopy), ISBN 9781627052344 (eBook), April 2014.
• Digital System Verification: A Combined Formal Methods and Simulation Framework, Morgan & Claypool Publishers, San Rafael, California, ISBN 9781608451784 (hardcopy), ISBN 9781608451791 (eBook), February 2010, (with L. Li).
• Multiple-Valued Logic Concepts and Representations, Morgan & Claypool Publishers, San Rafael, California, ISBN 10-1598291904 (hardcopy), 10-1598291912 (eBook), January 2008, (with D. M. Miller).
• Introduction to Logic Synthesis Using Verilog HDL, Morgan & Claypool Publishers, San Rafael, California, ISBN 10-1598291068 (hardcopy), ISBN 10-1598291076 (eBook), November 2006, (with R. B. Reese).
• Spectral Techniques in VLSI CAD, Kluwer Academic Publishers, Boston, Massachusetts, ISBN 0-7923-7433-9, July 2001 (with R. Drechsler and D. M. Miller).

BOOK CHAPTERS AND ENCYCLOPEDIA  ARTICLES

• Computng the PPRM/ANF: Functional Methods, Chapter 1 in Advances in the Boolean Domain, Cambridge Scholars Publishing, Cambridge, UK, Bernd Steinbach, Editor, ISBN: 978-1-5275-8872-1, September 2022, (with D.K. Houngninou and D.M. Miller).
• Extracting PPRM/ANF From a Circuit Netlist, Chapter 2 in Advances in the Boolean Domain, Cambridge Scholars Publishing, Cambridge, UK, Bernd Steinbach, Editor, ISBN: 978-1-5275-8872-1, September 2022, (with D.K. Houngninou and D.M. Miller).
• Keyboard Dynamics, Article in the Encyclopedia of Cryptography, Security and Privacy, 3rd edition, S. Jajodia, P. Samarati, and M. Yung, Editors, Springer, Berlin, Heidelberg, February 7, 2021, <a href="https://doi.org/10.1007/978-3-642-27739-9_783-2.">https://doi.org/10.1007/978-3-642-27739-9_783-2</a>.
• Foreward, pp. xix - xxii, Further Improvements in the Boolean Domain, Cambridge Scholars Publishing, Cambridge, UK, Bernd Steinbach, Editor, 2018, ISBN 13-978-1-5275-0371-7; 10-1-5275-0371-2; January 1, 2018.
• A Vector Space Method for Boolean Networks, Chapter 1, Section 1.1, in Problems and New Solutions in the Boolean Domain, Cambridge Scholars Publishing, Cambridge, UK, Bernd Steinbach, Editor, 2015, ISBN 13-978-1-4438-8947-6; 10-1-4438-8947-4, pp. 3-50, January 5, 2016.
• Boolean Function Spectra and Circuit Probabilities, Chapter 4, Section 4.1, in Problems and New Solutions in the Boolean Domain, Cambridge Scholars Publishing, Cambridge, UK, Bernd Steinbach, Editor, 2015, ISBN 13-978-1-4438-8947-6; 10-1-4438-8947-4, January 5, 2016, pp. 269-286, (with Micah A. Thornton).
• The Best of IEEE-USA Insight: On Licensing Software Engineers, Article Reprints in Parts I, II, and III, IEEE-USA Publishing, Washington D.C., compiled by P. A. Laplante, Georgia C Stelluto, editor, 2015.
• Quantum Computing Approach for Alignment-free Sequence Search and Classification, Chapter 17 in Multidisciplinary Computational Intelligence Techniques: Applications in Business, Engineering, and Medicine, S. Ali, N. Abbadeni, and M. Batouche, Editors, IGI-Global Press, pp. 279-300, May 2012, ISBN 978-1-4666-1830-5 (hardcopy), ISBN 978-1-4666-1831-2 (eBook), (with R. Kotamarti and M.H. Dunham).
• Licensing Professional Software Engineers in the United States of America, Article in the Encyclopedia of Software Engineering, Taylor & Francis, New York, DOI: 10.1081/E-ESE, ISBN:1-4200-5977-7; eISBN: 1-4200-5978-5, Published online: April 24, 2012, pp. 1-8, (with P. A. Laplante).
• Keystroke Dynamics, Article in the Encyclopedia of Cryptography and Security, 2nd edition, H. C. A. van Tilborg and S. Jajodia, Editors, Springer Publishers, pp. 688-691, November 2011, ISBN 978-1-4419-5905-8.
• Multiprocessor Memory Resource Estimation, Chapter 10 in Parallel and Distributed Systems: Architectures, Tools and Algorithms, Jose Aguilar, Editor, IIIS Publishers, ISBN 980-07-5956-5, July 2001 (with D. L. Andrews).
• Computer-Aided Engineering and Design, Chapter 8 in ADVANCED ELECTRONIC PACKAGING: With Emphasis on Multi-Chip Modules, 1st edition, W. D. Brown, Editor, IEEE Press, Piscataway, New Jersey, ISBN 0-7803-4700-5, 1999, (with D. L. Andrews, J. M. Conrad and M. D. Glover).
• Microprocessor Systems, Article in the Encyclopedia of Life Support Systems, EOLSS Publishers Co. Ltd., March 2003.

PATENTS

• Systems and Methods for Multi-Source True Random Number Generators, Including Multi-Source Entropy Extractor Based Quantum Photonic True Random Number Generators, U.S. Patent 11,989,532, May 21, 2024, (continuation of U.S. 11,645,044), U.S. Patent Application 18/190,848, Pub. Date August 3, 2023, filed March 27, 2020, Pub. No. 2023/0244451, claiming priority from: Method and System for Constructing a Multi-source Entropy Extractor-based Quantum Photonic TRNG, U.S. Provisional Patent, Application 62/822,232, filed March 22, 2019, (Co-inventor with D.L. MacFarlane, W.V. Oxford, and M.A. Thornton).
• Systems and Methods for Controlled Quantum Information Processing Operation with Trans-radix Basis Components, U.S. Patent 11,868,848, January 9, 2024, U.S. Patent Application 17/230,251, filed April 15, 2021, Pub. No. 2021/0365825, Pub. Date November 25, 2021, claiming priority from U.S. Provisional Patent 63/027,056, filed May 19, 2020, (sole inventor).
• Systems and Methods for Preservation of Qubits, U.S. Patent 11,657,313, May 23, 2023, (continuation of 10,878,333), U.S. Patent Application No. 17/103,394, filed November 24, 2020, Pub. No. 2021/0103850, Pub. Date April 8, 2021, claiming priority from: Quantum State Oscillators and Methods for Operation and Construction of Same, U.S. Provisional Patent No. 62/491,815, filed April 28, 2017, (Co-inventor with D.L. MacFarlane, T.P. LaFave, Jr., and W.V. Oxford).
• Systems and Methods for Multi-Source True Random Number Generators, Including Multi-Source Entropy Extractor Based Quantum Photonic True Random Number Generators, U.S. Patent 11,645,044, May 9, 2023, U.S. Patent Application No. 16/825,449, filed March 20, 2020, Pub. No. 2020/0301670, claiming priority from: Method and System for Constructing a Multi-source Entropy Extractor-based Quantum Photonic TRNG, U.S. Provisional Patent, Application 62/822,232, filed March 22, 2019, (Co-inventor with D.L. MacFarlane, W.V. Oxford, and M.A. Thornton).
• Detecting Malicious Software using Sensors, U.S. Patent 11,586,737, February 21, 2023, (continuation of 11,042,638), Application 17/350,824, Pub. no. 2021/0312049, filed June 22, 2021, Priority date November 14, 2017, (Co-inventor with M.A. Taylor and K.N. Smith).
• Control System Anomaly Detection using Neural Network Consensus, U.S. Patent 11,546,205, January 3, 2023, Application 17/837,472, filed June 10, 2022, U.S. Provisional Patent 63/211,281, filed June 16, 2021, (Co-inventor with E.C. Larson, T.W. Manikas, M.A. Taylor, A. Sinha, N. Srirama).
• Generating Upsampled Signal from Gyroscope Data, U.S. Patent 11,397,083, July 26, 2022, Application No. 16/702,116, filed December 6, 2019, claiming priority from: Method and System for Increasing the Effective Sample Rate of a Sampled Signal, Provisional Application No. 62/776,238, filed December 6, 2018, (Co-inventor with E.C. Larson, I. Johnson, T. Siems, and E. Gabrielsen).
• Systems and Methods for Quantum Coherence Preservation of Qubits, U.S. Patent 11,080,614, August 3, 2021, U.S. Patent Application, No. 15/832,285, filed December 5, 2017, Pub. No. US2018/0157986, Pub. Date June 7, 2018, claiming priority from: Bell State Oscillator and Applications for Same, U.S. Provisional Patent 62/430,501, filed December 6, 2016, (Co-inventor with W.V. Oxford, D.L. MacFarlane, and T.P. LaFave, Jr.).
• Detecting Malicious Software using Sensors, U.S. Patent 11,042,638, June 22, 2021, Application, No. 15/812,663, filed November 14, 2017, Pub. No. 2020/0279043, Pub. Date September 3, 2020, (Co-inventor with M.A. Taylor and K.N. Smith).
• Systems and Methods for Preservation of Qubits, U.S. Patent 10,878,333, December 29, 2020, (continuation of 10,579,936), Application No. 16/748,481, filed January 21, 2020, Pub. No. 2020/0160206, Pub. Date May 21, 2020, claiming priority from: Quantum State Oscillators and Methods for Operation and Construction of Same, U.S. Provisional Patent No. 62/491,815, filed April 28, 2017, (Co-inventor with D.L. MacFarlane, T.P. LaFave, Jr., and W.V. Oxford).
• Systems and Methods for Preservation of Qubits, U.S. Patent 10,579,936, March 3, 2020, Application No. 15/965,286, filed April 27, 2018, Pub. No. 2018/0314969, Pub. Date November 1, 2018, claiming priority from: Quantum State Oscillators and Methods for Operation and Construction of Same, U.S. Provisional Patent No. 62/491,815, filed April 28, 2017, (Co-inventor with D.L. MacFarlane, T.P. LaFave, Jr. and W.V. Oxford).
• Squaring Circuit, U.S. Patent 9,684,489, June 20, 2017, Application No. 13/601,709, Filed August 31, 2012, Pub No. 2014/0067893, Filed March 6, 2014, Filed August 31, 2012, (Co-inventor with S. Gupta).
• Method for Subject Classification Using a Pattern Recognition Input Device, U.S. Patent 9,329,699, May 3, 2016, Application No. 13/279,279, Filed October 22, 2011, Claiming priority from provisional patent application 61/405,988, Filed October 22, 2010, (Co-inventor with J.D. Allen and J.J. Howard).
• Single Clock Distribution Network for Multi-Phase Clock Integrated Circuits, U.S. Patent 8,847,625, September 30, 2014, Application No. 13/769,313, Filed 16 February, 2013, Claiming priority from provisional patent application 61/599,598, Filed 16 February 2012, (Co-inventor with R. Menon).
• Determining a Table Output of a Table Representing a Hierarchical Tree for an Integer Valued Function, U.S. Patent 7,962,537, June 14, 2011, Application No. 11/768,742, Filed June 26, 2007, Pub. No. 2008/0005211, Pub. Date January 3, 2008, claiming priority from U.S. Provisional Patent 60/816,529, Filed June 26, 2006, Filed June 26, 2007, (Co-inventor with D.W. Matula, A. Fit-Florea, and L. Li).
• Method for Early Evaluation in Micropipeline Processors, U.S. Patent 7,043,710, May 9, 2006, Application No. 10/774,599, Filed February 10, 2004, Pub. No. 2004/0225699, Pub. Date November 11, 2004, claiming priority from U.S. Provisional Patent 60/446,987, Filed February 13, 2003, (Co-inventor with R.B. Reese).
• Systems and Methods for Implementing Structures for Physical Unclonable Functions, Application No. 18/364,515, Filed August 3, 2023, Pub. No. 2024/0223361, Pub. Date July 4, 2024, claiming priority from U.S. Provisional Patent 63/395,736, filed August 5, 2022, (Co-inventor with D.L. MacFarlane, W.V. Oxford, H. Shahoei, E. Stewart and S. Heinrich-Barna).
• System and Method for Remote Probabilistic Secret Key Distribution, Application No. 18/595,747, Filed March 5, 2024, claiming priority from U.S. Provisional Patent 63/489,617, Filed March 10, 2023, (Co-inventor with W.V. Oxford).
• Systems and Methods for RF Emitter Location with Automatic UAS Array Reconfiguration, Application No. 18/226,663, Filed July 26, 2023, Pub. No. 2024/0036153, Pub. Date February 1, 2024, claiming priority from U.S. Provisional Patent 63/369,911, Filed July 29, 2022, (Co-inventor with E.C. Larson and M.A. Bigham).
• Systems and Methods for Hybrid Physical Unclonable Functions, Notice of Allowance received June 10, 2024, Application No. 17/729,416, Filed April 26, 2022, Pub. No. 2022/0376934, Pub. Date November 24, 2022, claiming priority from Provisional Patent, 63/180,877, Filed April 28, 2021, (Co-inventor with D.L. MacFarlane and W.V. Oxford).
• Systems and Methods for Efficient Photonic Heralded Quantum Computing Systems, Application No. 17/468,358, Filed September 7, 2021, Pub. No. 2022/0076155, Pub. Date March 10, 2022, claiming priority from: Dual Rail Quantum Photonic Circuitry, U.S. Provisional Patent 63/075,369, Filed September 8, 2020, (Co-inventor with D.L. MacFarlane and W.V. Oxford).
• Systems and Methods for Reprovisionable Photonic PUFs, U.S. Provisional Patent 63/491,496, Filed March 21, 2023, (Co-inventor with W.V. Oxford, D.L. MacFarlane and S. Heinrich-Barna).
• Systems and Methods for Computing an Inverse Hash Function, U.S. Provisional Patent 63/415,508, Filed October 12, 2022, (Co-inventor with J.M. Henderson, E.R. Henderson and W.V. Oxford).
• Systems and Methods for Implementing Photonic Quantum Storage, U.S. Provisional Patent, Application No. 62/613,262, filed January 3, 2018, Abandoned, (Co-inventor with W.V Oxford, D.L. MacFarlane, T.P. LaFave, Jr., and J.S. Gable).
• Systems and Methods for Implementing Structures for Physical Unclonable Functions, World Intellectual Property Organization (WIPO), Pub. No. WO 2024/030522, Pub. Date February 2, 2024, Application No. PCT/US2023/029359, Filing Date August 3, 2023, claiming priority from U.S. Provisional Patent 63/395,736, Filed August 5, 2022, (Co-inventor with D.L. MacFarlane, W.V. Oxford, H. Shahoei, E.J. Stewart, and S.K. Heinrich-Barna).
• Systems and Methods for Generating and Implementing a Reversible Hash Circuit, World Intellectual Property Organization (WIPO), Pub. No. WO 2024/081576, Pub. Date April 18, 2024, Application No. PCT/US2023/076349, Filing Date October 9, 2023, claiming priority from U.S. Provisional Patent 63/415,508, Filed October 12, 2022, (Co-inventor with E.R. Henderson, J.M. Henderson and W.V. Oxford).
• Control System Anomaly Detection using Neural Network Consensus, World Intellectual Property Organization (WIPO), Pub. No. WO 2022/265923, Pub. Date December 22, 2022, Application No. PCT/US2022/032934, Filing Date: June 10, 2022, claiming priority from U.S. Provisional Patent 63/211,281, Filed June 16, 2021 and U.S. Provisional Patent 63/275,759, Filed November 4, 2021, (Co-inventor with E.C. Larson, T.W. Manikas, M. Taylor, A. Sinha and N. Srirama).
• Systems and Methods for Hybrid Physical Unclonable Functions, World Intellectual Property Organization (WIPO), Pub. No. WO 2022/232115, Pub. Date November 3, 2022, Application No. PCT/US22/026304, Filed April 26, 2022, claiming priority from U.S. Provisional Patent 63/180,877, Filed Aprl 28, 2021, (Co-inventor with D.L. MacFarlane and W.V. Oxford).
• Systems and Methods for Controlled Quantum Information Processing Operation with Trans-radix Basis Components, World Intellectual Property Organization (WIPO), Pub. No. WO 2021/236271, Pub. Date November 25, 2021, Application No. PCT/US2021/027795, Filed April 16, 2021, claiming priority from U.S. Provisional Patent 63/027,056, Filed May 19, 2020, (M.A. Thornton is sole inventor).
• Systems and Methods for Multi-Source True Random Number Generators, World Intellectual Property Organization (WIPO), Pub. No. WO 2020/197944, Pub. Date October 1, 2020, Application No. PCT/US2020/023684, Filed March 19, 2020, claiming priority from U.S. Provisional Patent 62/822,232, Filed March 22, 2019, (Co-inventor with D.L. MacFarlane, W.V. Oxford and M.A. Thornton).
• Systems and Methods for Quantum Coherence Preservation of Qubits, World Intellectual Property Organization (WIPO), Pub. No. WO 2018/222311, Pub. Date December 6, 2018, Application No. PCT/US2018/029888, Filed April 27, 2018, claiming priority from U.S. Provisional Patent 62/491,815, Filed April 28, 2017, (Co-inventor with W.V. Oxford, D.L. MacFarlane and T.P. LaFave, Jr.).
• Systems and Methods for Quantum Coherence Preservation of Qubits, World Intellectual Property Organization (WIPO), Pub. No. WO 2018/106702, Pub. Date June 14, 2018, Application No. PCT/US2017/064731, Filed December 5, 2017, claiming priority from U.S. Provisional Patent 62/430,501, Filed December 6, 2016, (Co-inventor with W.V. Oxford, D.L. MacFarlane and T.P. LaFave, Jr.).

NATIONAL/INTERNATIONAL CONFERENCES

• Controller Area Network (CAN) Bus Transceiver with Enhanced Rail Converter, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 11, 2024, (to appear, with W. Chen, C. Hong, X. Wen and P. Gui).
• A Photonic Physically Unclonable Function's Resilience to Multiple-Valued Machine Learning Attacks, IEEE Symposium on Multiple-Valued Logic (ISMVL), May 28-30, 2024, pp. 167-172, (with J.M. Henderson, E.R. Henderson, C.A. Harper, H. Shahoei, W.V. Oxford, E.C. Larson and D.L. MacFarlane).
• Automated Quantum Circuit Generation for Computing Inverse Hash Functions, SPIE Proceedings 13208, DCS24 SPIE Quantum Information Science, Sensing, and Computation XVI, April 24, 2024, 130280D (12 pp.), published June 7, 2024, https://doi.org/10.1117/12.3012744, (with E.R. Henderson, J.M. Henderson and W.V. Oxford).
• Towards a Photonic Integrated Circuit Realization of Polarization-Encoded Qubits, SPIE Proceedings Volume 13208, DCS24 SPIE Quantum Information Science, Sensing, and Computation XVI, April 24, 2024, 130280E (6 pp.), published June 7, 2024, https://doi.org/10.1117/12.3016742, invited paper, (with D.L. MacFarlane, A. Helmy, H. Shahoei, T. LaFave, E. Stewart and W.V. Oxford).
• Designing a Photonic Physically Unclonable Function having Resilience to Machine Learning Attacks, SPIE Proceedings Volume 13208, DCS24 SPIE Quantum Information Science, Sensing, and Computation XVI, April 24, 2024, 130280B (14 pp.), published June 7, 2024, https://doi.org/10.1117/12.3013126, invited paper, (with E.R. Henderson, J.M. Henderson H. Shahoei, W.V. Oxford, E.C. Larson and D.L. MacFarlane).
• Learnable Statistical Moments Pooling for Automatic Modulation Classification, IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), April 14-19, 2024, pp. 8981-8985, (with C.A. Harper and E.C. Larson).
• Impacts of Synthetically Generated Data on Trackformer-based Multi-object Tracking, IEEE Applied Imagery Pattern Recognition Workshop (AIPR), September 27-29, 2023, 7 pp., (with M. Lee, C. Harper, W. Flinchbaugh and E.C. Larson).
• Using Time Series Clustering to Inform Multimodal CNN Architectures, IEEE Applied Imagery Pattern Recognition Workshop (AIPR), September 27-29, 2023, 8 pp., (with J. Sylvester, M. Lee, D.C. Ellis and E.C. Larson).
• Assessing Random Bit Generator Quality with Granger Causality Extensions, (video), International Cryptographic Modules Conference (ICMC), September 20-22, 2023, (refereed abstract, presentor is Micah A. Thornton, with Micah A. Thornton, W.V. Oxford, J. Gable, J. Sylvester, M. Lee and E.C. Larson).
• Multiple-Valued Logic Physically Unclonable Function in Photonic Integrated Circuits, IEEE Symposium on Multiple-Valued Logic (ISMVL), May 22-24, 2023, pp. 184-189, (with D.L. MacFarlane, H. Shahoei, I.G. Achu, E. Stewart and W.V. Oxford).
• City Scale Autonomy Learning, SPIE 12525, Geospatial Informatics XIII, April 30-May 4, 2023, 125250M (4 pp.), publication date June 15, 2023, (with D.L. Young and S. Gibbs).
• A Programmable True Random Number Generator using Commercial Quantum Computers, SPIE 12517, Quantum Information Science, Sensing, and Computation XV, April 30-May 4, 2023, 1251705 (15 pp.), publication date June 13, 2023, (with A. Sinha, E.R. Henderson, J.M Henderson and E.C. Larson).
• Automated Quantum Oracle Synthesis with a Minimal Number of Qubits, SPIE 12517, Quantum Information Science, Sensing, and Computation XV, April 30-May 4, 2023, 1251706 (18 pp.), publication date June 13, 2023, (with J.M. Henderson, E.R. Henderson, A. Sinha and D.M. Miller).
• Adding RF Situational Awareness to Robotic Simulation Systems, SPIE 12540, Autonomous Systems: Sensors, Processing and Security for Ground, Air, Sea and Space Vehicles and Infrastructure, April 30-May 4, 2023, 125009 (16 pp.), publication date June 13, 2023, (with D.L. Young and S. Gibbs).
• Cooperative UAS Geolocation of Emitters with Multi-Sensor-bounded Timing and Localization Error, IEEE Aerospace Conference (AERO), March 4-11, 2023, 13 pp., (with C. Peters).
• Data Leakage in Isolated Virtualized Enterprise Computing Systems, International Conference on Information Systems Security and Privacy (ICISSP), February 22-23, 2023, pp. 118-123, (with Z. Wolf and E.C. Larson).
• Automated Quantum Memory Compilation with Improved Dynamic Range, International Conference for High Performance Computing, Networking, Storage, and Analysis (SC22), International Workshop on Quantum Computing software (QSC22), November 13, 2022, 14 pp., arXiv version, (with A. Sinha, E.R. Henderson and J.M. Henderson).
• SMU-DDI Cyber Autonomy Range, IEEE Applied Imagery Pattern Recognition Workshop (AIPR), October 11-12, 2022, 5 pp., (with D.L. Young, M. Bigham, M. Bradbury and E.C. Larson).
• An Embedded Malware Detection System using a Support Vector Machine, International Conference on Embedded Systems, Cyber-physical Systems and Applications (ESCS) in the World Congress in Computer Science, Computer Engineering and Applied Computing (CSCE), proceedings published in Springer Nature-Transactions on Computational Science and Computational Intelligence, July 25-28, 2022, 7 pp., (in press, with R. Oshana, M. Caraman and N. Srirama).
• A Side Channel Attack Detection System using Processor Core Events and a Support Vector Machine, IEEE Mediterranean Conference on Embedded Computing (MECO), June 7-10, 2022, pp. 176-183, (with R. Oshana and M. Caraman).
• Controller Area Network (CAN) Bus Transceiver with Authentication Support, IEEE International Symposium on Circuits and Systems (ISCAS), May 28-June 1, 2022, pp. 1328-1331, (with X. Wen, T. Fu, J. Liu, R. Hua, and P. Gui).
• Quantum Multiple Valued Kernel Circuits, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 18-20, 2022, pp. 1-8, (with A. Sinha).
• General Process Detection Through Physical Side Channel Characterization, IEEE Systems Conference (SYSCON), April 25-28, 2022, pp. 1-8, (with M. Taylor and E.C. Larson).
• Side Channel Identification using Granger Time Series Clustering with Applications to Control Systems, International Conference on Information Systems Security and Privacy (ICISSP), February 9-11, 2022, pp. 290-298, (with M. Lee, J. Sylvester, S. Aggarwal, A. Sinha, M. Taylor, N. Srirama, and E.C. Larson).
• SNR-Boosted Automatic Modulation Classification, IEEE Asilomar Conference on Signals, Systems, and Computers (ASILOMAR), October 31-November 3, 2021, pp. 372-375, (with C. Harper, A. Sinha and E.C. Larson).
• Industrial Control System Anomaly Detection using Convolutional Neural Network Consensus,  IEEE Conference on Control Technology and Applications (CCTA), August 9-11, 2021, pp. 693-700, (with A. Sinha, M.A. Taylor, N. Srirama, T.W. Manikas, E.C. Larson, and M.A. Thornton).
• Rapid Ransomware Detection Through Side Channel Exploitation, IEEE Conference on Cyber Security and Resilience (CSR), July 26-28, 2021, pp. 47-54, (with M.A. Taylor and E.C. Larson).
• Real-Time Edge Processing Detection of Malicious Attacks using Machine Learning and Processor Core Events, IEEE Systems Conference (SYSCON), March 22, 2021, pp. 1-8, (with R. Oshana, E.C. Larson and X. Roumegue).
• A Quantum Photonic TRNG based on Higher-radix Logic, IEEE International Symposium on Multiple-Valued Logic (ISMVL), November 10, 2020, pp. 164-169, (with K.N. Smith and D.L. MacFarlane).
• Fast Minimization of Polynomial Decomposition using Fixed-polarity Pascal Transforms, IEEE International Symposium on Multiple-Valued Logic (ISMVL), November 11, 2020, pp. 259-264, (with K.N. Smith and D.M. Miller).
• A Quantum Photonic TRNG based on Higher-radix Logic, IEEE International Symposium on Multiple-Valued Logic (ISMVL), November 10, 2020, pp. 164-169, (with K.N. Smith and D.L. MacFarlane).
• Introduction to Quantum Computation Reliability, IEEE International Test Conference (ITC), November 3-5, 2020, pp. 1-10, online proceedings, (invited, online, video).
• Enhanced Automatic Modulation Classification using Deep Convolutional Latent Space Pooling, IEEE Asilomar Conference on Signals, Systems, and Computers (ASILOMAR), paper MO2-1-4 (online), November 1-4, 2020, pp. 162-165 (with C.A. Harper, L. Lyons, M.A. Thornton, and E.C. Larson).
• Entangled State Preparation for Non-Binary Quantum Computing, IEEE International Conference on Rebooting Computing (ICRC), November 6-8, 2019, pp. 71-79, (with K.N. Smith).
• Fixed Polarity Pascal Transforms with Computer Algebra Applications, IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing (PACRIM), August 21-23, 2019, pp. 1-8, (with K.N. Smith).
• Quantum Logic Synthesis with Formal Verification, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 4-7, 2019, pp. 73 - 76, (with K.N. Smith).
• A Discussion on Blockchain Software Quality Attribute Design and Tradeoffs, International Conference on Emerging Topics in Computing (iCETiC), August 19-20, 2019, Springer Nature, LNICST vol. 285, pub. date: July 14, 2019, pp. 19-28, (with J. Medellin, best paper award).
• A Quantum Computational Compiler and Design Tool for Technology-specific Targets, IEEE International Symposium on Computer Architecture (ISCA), June 22-26, 2019, pp. 579 - 588, ACM digital library, (with K.N. Smith).
• Using ZDDs in the Mapping of Quantum Circuits, Quantum Physics and Logic Conference (QPL), June 10-14, 2019, pp. 1 - 11, (with K.N. Smith, M. Soeken, B. Schmitt, and G. De Micheli), arXiv:1901.02406.
• Entanglement in Higher-Radix Quantum Systems, IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 114-119, May 21-23, 2019, (with K.N. Smith), arXiv:1906.00491.
• Task Value Calculus: Multi-objective Tradeoff Analysis using Multiple-valued Decision Diagrams, IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 126-131, May 21-23, 2019, (with T. Giallanza, E. Gabrielsen, M.A. Taylor, and E.C. Larson).
• Quantum Photonic TRNG with Dual Extractor, International Conference on Networked Systems/Workshop on Quantum Technology and Optimization Problems (NetSys/QTOP), Springer-Verlag LNCS 11413, March 18-21, 2019, pp. 171-182, (with D.L. MacFarlane), presentation video.
• Performance Characteristics of Two Blockchain Consensus Algorithms in a VMware Hypervisor, in proc. International Conference on Grid, Cloud, and Cluster Computing (GCC), July 30, 2018, (with J. Medellin).
• Simulating Resource Consumption in Three Blockchain Consensus Algorithms, in proc. International Conference on Modeling, Simulation and Visualization Methods (MSV), July 30, 2018, (with J. Medellin).
• A 2.56 Gbps Asynchronous Serial Transceiver with Embedded 80 Mbps Secondary Data Transmission Capability in 65nm CMOS, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 10-12, 2018, pp. 360 - 363, (with X. Wang, T. Liu, S. Guo, and P. Gui).
• Multiple-Valued Random Digit Extraction, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 16-18, 2018, pp. 162-167, (with Micah A. Thornton).
• A Radix-4 Chrestenson Gate for Optical Quantum Computation, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 16-18, 2018, pp. 260-265, (with K.N. Smith, T.P. LaFave, Jr., and D. MacFarlane).
• Sensor-Based Ransomware Detection, Future Technologies Conference (FTC), November 29-30, 2017, pp. 794-801, (with M.A. Taylor and K.N. Smith).
• Simulation of Switching Circuits using Transfer Functions, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 6-9, 2017, pp. 511-514, (with D.K. Houngninou).
• Automated Markov-chain Based Analysis for Large State Spaces, IEEE International Systems Conference (SYSCON), April 24-27, 2017, pp. 306-313, (with K.N. Smith, M.A. Taylor, A.A. Carroll, and T.W. Manikas).
• Demographic Group Prediction Based on Smart Device User Recognition Gestures, IEEE International Conference on Machine Learning and Applications (ICMLA), pp. 100-107, December 18-20, 2016, (with A. Alharbi).
• Implementation of Switching Circuit Models as Transfer Functions, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2167-2170, May 22-25, 2016, (with D.K. Houngninou).
• Reliability Block Diagram Extensions for Non-Parametric Probabilistic Analysis, IEEE International Systems Conference (SYSCON), pp. 927-932, April 18-21, 2016, (with P.C. Davis and T.W. Manikas).
• Demographic Group Classification of Smart Device Users, IEEE International Conference on Machine Learning and Applications (ICMLA), pp. 481-486, December 9-11, 2015, (with A. Alharbi).
• An Improved Methodology for System Threat Analysis using Multiple-Valued Logic and Conditional Probabilities, Society for Design and Process Science (SDPS), November 1-5, 2015, (with T.W. Manikas and S. Nagayama).
• A Multiple-Valued Logic Synthesis Tool for Optical Computing Elements, IEEE Dallas Circuits and Systems Conference (DCAS), pp. 1-4, paper 38-2.3, October 12-13, 2015, (with K.N. Smith).
• Edge Reduction for EVMDDs to Speed Up Analysis of Multi-State Systems, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 18-20, 2015, pp. 170-175, (with S. Nagayama, T. Sasao, J.T. Butler, and T.W. Manikas).
• System Probability Distribution Modeling using MDDs, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 19-21, 2014, pp. 196-201, (with T.W. Manikas, S.A. Szygenda, and S. Nagayama).
• Analysis Methods of Multi-State Systems Partially having Dependent Components using Multiple-Valued Decision Diagrams, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 19-21, 2014, pp. 190-195, (with S. Nagayama, T. Sasao, J.T. Butler, and T.W. Manikas).
• Embedded and Real-time Systems Classes in Traditional and Distance Format, Frontiers in Education Conference (FIE), October 23-26, 2013, pp. 1379-1385, (with T.W. Manikas and P.A. Laplante).
• Low Power Floating-Point Multiplication and Squaring Units with Shared Circuitry, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 4, 2013, pp. 1395-1398, (with J. Moore and D.W. Matula).
• A Transfer Function Model for Ternary Switching Logic Circuits, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 24-25, 2013, pp. 103-108.
• Ternary Logic Network Justification Using Transfer Matrices, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 24-25, 2013, pp. 310-315, (with J. Dworak).
• Spectral Response of  Ternary Logic Netlists, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 24-25, 2013, pp. 109-116, (with T.W. Manikas).
• Using the Asynchronous Paradigm for Reversible Sequential Circuit Implementation, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 14-16, 2012, pp. 305-310, (with D.Y. Feinstein).
• Global Multiple-valued Clock Approach for High-performance Multi-phase Clock Integrated Circuits, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 14-16, 2012, pp. 19-24, (with R.P. Menon).
• Modeling Medical System Threats with Conditional Probabilities using Multiple-valued Logic Decision Diagrams, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 14-16, 2012, pp. 244-249, (with T.W. Manikas and D.Y. Feinstein).
• Uncle-An RTL Approach to Asynchronous Design, IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 7-9, 2012, pp. 65-72, (with R.B. Reese and S.A. Smith).
• Faculty and Student Perceptions of Online Learning in Engineering Education, ASEE Annual Conference, June 10-13, 2012, (with L. Kinney and M. Liu).
• On the Skipped Variables of Quantum Multiple-valued Decision Diagrams, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 23-25, 2011, pp. 164-168, (with D.Y. Feinstein).
• Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities, IEEE International Symposium on Mulitple-Valued Logic (ISMVL), May 23-25, 2011, pp. 263-267, (with T. Manikas and D.Y. Feinstein).
• A Compliance Framework to Optimize Product Development in a Regulated Industry, Intellectbase International Consortium Academic Conference, March 25-26, 2011, (with D.M. Easton).
• Spectral Analysis of Digital Logic Circuit Netlists, International Conference on Computer Aided Systems Theory (EUROCAST), February 6-11, 2011, pp. 414-415.
• Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits, IEEE International Symposium on Mulitple-Valued Logic (ISMVL), May 26-28, 2010, pp. 128-133, (with S. Datla).
• Cyber Threat Trees for Large System Threat Cataloging and Analysis, IEEE Systems Conference (SYSCON), April 5-6, 2010, pp. 610-615, (with P. Ongsakorn, K. Turney, S. Nair, S. Szygenda, and T. Manikas).
• Large System Decomposition and Simulation Methodology using Axiomatic Analysis, IEEE International Systems Conference, (SYSCON), April 5-6, 2010, pp. 223-227, (with L. Spenner, P. Krier, S. Nair, S. Szygenda, and T. Manikas).
• An Axiomatic Analysis Approach for Large-Scale Disaster-Tolerant Systems Modeling, International Multi-Conference on Complexity, Informatics, and Cybernetics (IMIC10), International Conference on Computing, Communications and Control Technologies (CCCT), April 6-9, 2010, pp. 66-70, (best paper award, with T. Manikas, L. Spenner, P. Krier, S. Nair, and S. Szygenda).
• A Digital-to-Frequency Converter using Redundant Signed Binary Addition, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 2-5, 2009, pp. 495-498, (with W. Chen and P. Gui).
• A Low Power High Performance Radix-4 Approximate Squaring Circuit, IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), July 7-9, 2009, pp. 91-97, (with S. Datla and D.W. Matula).
• On the Guidance of Reversible Logic Synthesis by Dynamic Variable Ordering, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 21-23, 2009, pp. 132-138, (with D. Feinstein).
• Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 21-23, 2009, pp. 256-261, (with S. Datla, L. Hendrix, and D. Henderson).
• A Low Power Radix-4 Dual Recoded Integer Squaring Implementation for use in Design of Application Specific Arithmetic Circuits, IEEE Asilomar Conference on Signals, Systems, and Computers (ASILOMAR), October 26-29, 2008, pp. 1819-1822, (with J. Moore and D.W. Matula).
• Quantum Logic Implementation of Unary Arithmetic Operations, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 22-23, 2008, pp. 202-207, (with L. Spenner, D. W. Matula, and D. M. Miller).
• On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams, IEEE International Symposium on Multiple Valued Logic (ISMVL), May 22-23, 2008, pp. 138-143, (with D. Y. Feinstein and D. M. Miller).
• Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits, Proceedings of the IEEE/ACM Design, Automation and Test in Europe (DATE), March 10-14, 2008, pp. 1378-1381, (with D. Y. Feinstein and D. M. Miller).
• UML to SystemVerilog Synthesis for Embedded System Models with Support for Assertion Generation, Proceedings of the ECSI Forum on Design Languages, September 18-20, 2007, Paper 10 on CD-ROM, (with L. Li and F. Coyle).
• ESOP-based Toffoli Gate Cascade Generation, Proceedings of the IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, August 22-24, 2007, pp. 206-209, (with K. Fazel and J.E. Rice).
• Axiomatic Design in the Biomedical Device Industry, Proceedings of the 11^th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI), July 8-11, 2007, (with D. Easton, V.S.S. Nair, and J. Stracener).
• Axiomatic Design Process for Disaster Tolerance, Proceedings of the 11^th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI), July 8-11, 2007, (with D. Easton and V.S.S. Nair).
• Variable Reordering and Sifting for QMDD, IEEE International Symposium on Multiple Valued Logic (ISMVL), May 14-16, 2007, electronic proceedings, Session 2B, paper 1, (with D. Michael Miller and D.Y. Feinstein).
• Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL, IEEE International Symposium on Multiple Valued Logic (ISMVL), May 14-16, 2007, electronic proceedings, Session 8B, paper 2, (with M. Amoui, D. Grosse, and R. Drechsler).
• Techniques for Disaster Tolerant Information Technology Systems, IEEE Systems Conference, April 9-12, 2007, pp. 333-338, (with C.M. Lawler and S.A. Szygenda).
• Disaster Tolerant Systems Engineering for Critical Infrastructure Protection, IEEE Systems Conference, April 9-12, 2007, pp. 2-8, (with M.A. Harper and S.A. Szygenda).
• Performance Evaluation of a Novel Table Lookup Method and Architecture for Integer Functions, IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pp. 99-104, September 11-13, 2006, (with L. Li, A. Fit-Florea, and D.W. Matula).
• A Decision Diagram Package for Reversible and Quantum Circuit Simulation, IEEE Congress on Evolutionary Computation, IEEE World Congress on Computational Intelligence (WCCI), July 16-21, 2006, pp. 8597-8604 on Proceedings CD-ROM, (best paper of session, with D.M. Miller and D. Goodman).
• QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 17-20, 2006, pp. 30-30 on Proceedings CD-ROM, (with D.M. Miller).
• A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 17-20, 2006, pp. 33-33 on Proceedings CD-ROM, (electronic version only, with L. Li and M. Perkowski).
• A Digit Serial Algorithm for the Integer Power Operation, ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), April 30-May 2, 2006, pp. 302-307, (with L. Li and D.W. Matula).
• BDD-Based Conjunctive Decomposition Using a Genetic Algorithm and Dependent Variable Affinity, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 24-26, 2005, pp. 277-280, (with L. Li and S. Szygenda).
• Early Evaluation for Phased Logic Circuits Using BDDs and MVL, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 24-26, 2005, pp. 400-403, (with K. Fazel and R.B. Reese).
• A Survey and Comparison of Digital Logic Simulators, IEEE Mid-West Symposium on Circuits and Systems (MWSCAS), August 7-10, 2005, p. 156 (abstract), full paper on Proceedings CD-ROM, (with M. Gunes, F. Kocan, and S.A. Szygenda).
• Disaster Tolerant Computing and Communications, International Conference on Cybernetics and Information Technologies, Systems and Applications (CITSA 2005), and International Conference on Information Systems Analysis and Synthesis (ISAS), July 14-17, 2005, pp. 171-173, (invited paper, with S. Szygenda).
• IT Application Downtime, Executive Visibility and Disaster Tolerant Computing, International Conference on Cybernetics and Information Technologies, Systems and Applications (CITSA 2005), and International Conference on Information Systems Analysis and Synthesis (ISAS), July 14-17, 2005, pp. 165-170, (invited paper, with M. A. Harper and C. Lawler).
• Combining Simulation and Formal Verification for Integrated Circuit Design Validation, 9^th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI), July 10-13, 2005, pp. 92-97, (with L. Li and S. Szygenda).
• Lookup Table Structures for Multiplicative Inverses Modulo 2^k, IEEE Symposium on Computer Arithmetic (ARITH), June 27-29, 2005, pp. 130-135, (D.W. Matula and A. Fit-Florea).
• The Karhunen-Loève Transform of Discrete MVL Functions, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 18-21, 2005, pp. 194-199.
• Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2^k, IEEE Symposium on VLSI (ISVLSI), May 10-11, 2005, pp. 130-135, (with L. Li, A. Fit-Florea, and D.W. Matula).
• A Framework and Process for Curricular Integration and Innovation Using Project Based Interdisciplinary Teams, International Conference on Information Technology (ITCC), April 4-6, 2005, pp. 432-435, (with F.P. Coyle).
• From UML to HDL: a Model Driven Architectural Approach to Hardware-Software Co-Design, Information Systems: New Generations Conference (ISNG), April 4-6, 2005, pp. 88-93, (with F.P. Coyle).
• Static Variable Ordering in ZBDDs for Path Delay Fault Coverage Calculation, IEEE Mid-west Symposium on Circuits and Systems (MWSCAS), July 25-28, 2004, pp. I-509 - I-512, (with F. Kocan and M. Gunes).
• Test Vector Generation and Classification Using FSM Traversals, IEEE International Symposium on Circuits and Systems (ISCAS), May 23-26, 2004, pp. V-309 - V-312, (with R. Marczynski and S. Szygenda).
• Performance Enhancement in Phased Logic Circuits Using Automatic Slack Matching Buffer Insertion, ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), April 26-28, 2004, pp. 413-416, (K. Fazel, L. Li, R. B. Reese and C. Traver).
• A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), February 19-20, 2004, pp. 32-36, (with L. Li and S. Szygenda).
• Spectral Transforms of Mixed-radix MVL Functions, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 16-19, 2003, pp. 329-333.
• A Coarse-Grain Phased Logic CPU, IEEE International Symposium on Asynchronous Circuits & Systems (ASYNC), May 12-16, 2003, pp. 2-13, (with R. Reese and C. Traver).
• PLFire: A Visualization Tool for Asynchronous Phased Logic Designs, IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), March 3-7, 2003, pp. 1096-1097, (poster presentation, with K. Fazel and R. B. Reese).
• A Fine-grain Phased Logic CPU, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), February 20-21, 2003, pp. 70-79, (with R. B. Reese and C. Traver).
• Switching Activity Estimation of FSMs for Low Power Synthesis, IEEE International Symposium on Circuits and Systems (ISCAS), May 26-29, 2002, vol. IV, pp. 65-68, (with M. Kerttu, P. Lindgren and R. Drechsler).
• Chrestenson Spectrum Computation Using Cayley Color Graphs, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 15-18, 2002, pp. 123-128, (with D. M. Miller and W. Towsend).
• Efficient Adder Circuits Based on a Conservative Reversible Logic Gate, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), April 25-26, 2002, pp. 83-88, (with J. W. Bruce, L. Shivakumaraiah, P. S. Kokate and X. Li).
• Computing Walsh, Arithmetic and Reed-Muller Spectral Decision Diagrams Using Graph Transformations, Great Lakes Symposium on VLSI (GLSVLSI), April 18-19, 2002, pp. 178-183, (with W. Towsend, D. M. Miller and R. Drechsler).
• Multi-output Timed Shannon Circuits, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 47-52, April 25-26, 2002, (with R. Drechsler and D. Michael Miller).
• Generalized Early Evaluation in Self-timed Circuits, IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), pp. 255-259, March 4-8, 2002, (with K. Fazel, R. Reese and C. Traver).
• Fast and Efficient Equivalence Checking based on NAND-BDDs, IFIP International Conference on Very Large Scale Integration (VLSI-SOC), pp. 401-405, December 3-5, 2001, (with R. Drechsler).
• Cell Designs for Self-timed FPGAs, IEEE ASIC/SOC Conference (ASIC), pp.175-179, September 2001, (with C. Traver and R. Reese).
• Arithmetic Logic Circuits using Self-Timed Bit-Level Dataflow and Early Evaluation, IEEE International Conference on Computer Design (ICCD), pp. 18-23, September 23-26, 2001, ( with R. Reese and C. Traver).
• Application of a Hardware Synthesis Technique for Database Query Optimization, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 26-28, 2001, pp. 715-718, (with V. Komaragiri and R. Drechsler).
• Evolutionary Algorithm Approach for Symbolic FSM Traversals, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 26-28, 2001, pp. 506-509, (with R. Drechsler).
• Walsh Spectrum Computations Using Cayley Graphs, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 14-17, 2001, pp. 110-113, (with W. Townsend).
• Spectral Decision Diagrams Using Graph Transformations, IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), March 13-16, 2001, pp. 713-717, (with R. Drechsler).
• Low Power Optimization Technique for BDD Mapped Circuits, IEEE/IEICE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), January 30-February 2, 2001, pp. 615-621, (P. Lindgren, M. Kerrtu and R. Drechsler).
• Cache Resident Data Locality Analysis, ACM/IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), August 29-September 1, 2000, pp.539-546, (with Q. G. Samdani).
• MDD-based Synthesis of Multi-Valued Logic Networks, IEEE International Symposium for Multiple-Valued Logic (ISMVL), May 23-25, 2000, pp. 41-46, (with R. Drechsler and D. Wessels).
• Computation of Spectral Information from Logic Netlists, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 23-25, 2000,  pp. 53-58, (with  R. Drechsler).
• A Method for Approximate Equivalence Checking, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 23-25, 2000, pp. 447-452, (with R. Drechsler and W. Günther).
• Extracting spectral information from AND/OR representations, IEEE Electrotechnical and Computer Science Conference (ERK), September 23-25, 1999, pp. 27-32, ( with R. Drechsler and A. Žužek).
• SBDD Variable Reordering Based on Probabilistic and Evolutionary Algorithms, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 22-24, 1999, pp. 381-387, (with J. P. Williams, R. Drechsler, N. Drechsler and D. Wessels).
• Tradeoff Analysis of Integer Multiplier Circuits Implemented in FPGAs, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 22-24, 1999, pp. 301-304, (with J. Gaiche and J. Lemieux).
• Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities, IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), presentation poster, March 9-12, 1999, pp. 758-759, (with J. P. Williams, R. Drechsler and N. Drechsler).
• Modified Haar Transform Calculation Using Digital Circuit Output Probabilities, IEEE International Conference on Information, Communications & Signal Processing (ICICS), September 9-12, 1997, pp. 52 - 58, (invited paper).
• Applications of Circuit Probability Computation Using Decision Diagrams, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 20 - 22, 1997, pp. 683-687, (with R. P. Moore and J. C. Cordova).
• A Technique for Multiprocessor Memory Resource Estimation, World Multiconference on Systematics, Cybernetics and Informatics, July 7-11, 1997, Volume 1, pp. 212-218, (with J. D. Bullard and D. L. Andrews).
• Graph Analysis and Transformation Techniques for Run-Time Minimization in a Multi-Threaded Architecture, 30-th Hawaii International Conference on Systems Sciences (HICSS), January 1997, Volume 1, pp. 566-575, (with D. L. Andrews).
• Behavioral to Structural Translation in ESOP Form, IEEE International Verilog HDL Conference (IVL), March 1994, pp. 58-62, (best paper award with V. S. S. Nair)
• An Iterative Combinational Logic Synthesis Technique using Spectral Information, IEEE/ACM European Design Automation Conference (EURO-DAC), September 1993, pp. 358-363, (with V. S. S. Nair).

NATIONAL/INTERNATIONAL WORKSHOPS

• A Study of Extending Transformation-based Synthesis to Incompletely-specified Functions, Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design (RMW), pp. 1-8, May 24, 2023, (with D.M. Miller, unpublished workshop proceedings, abstract provided only).
• ANF Computation of Cryptographic Switching Functions using a Netlist Representation, Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design (RMW), pp. 1-11, May 10, 2021, (with D.K. Houngninou and D.M. Miller, unpublished workshop proceedings, abstract provided only).
• Rotation Primitives in Quantum Compilation, International Workshop on Quantum Compilation (IWQC, in conjunction with IEEE/ACM ICCAD), November 7, 2019, refereed abstract with presentation, (with K.N. Smith and J. Henderson).
• Fixed Polarity Pascal Transforms with Computer Algebra Applications, Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design (RMW), pp. 34-45, May 24, 2019, (with K.N. Smith, unpublished workshop proceedings, abstract provided only).
• Automated Mapping Methods for the IBM Transmon Devices, International Workshop on Post-Binary ULSI Systems (ULSI-WS), pp. 12-17, May 15, 2018, (with K.N. Smith).
• Minimizing Ancilla and Garbage Qubits in Reversible Functions, Southwest Quantum Information and Technology 20th Annual SQuInT Workshop (SQuInT), February 22-24, 2018, (with E. Gabrielsen).
• Single Qubit Quantum Ring Structures and Applications, Southwest Quantum Information and Technology 20th Annual SQuInT Workshop (SQuInT), February 22-24, 2018, (with K.N. Smith, D.L. MacFarlane, T.P. LaFave, Jr., and W.V. Oxford).
• MUSTANG-Q: A Technology Dependent Quantum Logic Synthesis and Compilation Tool, Design Automation for Quantum Computers Workshop, IEEE International Conference on Computer Aided Design (ICCAD-QCEDA), November 13-16, 2017, (refereed abstract and poster presentation, with K.N. Smith).
• On the Computation of Reed-Muller Spectra for Cryptography and Switching Theory Applications, Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design (RMW), May 24-25, 2017, (unpublished workshop proceedings, link to abstract only, with D.M. Miller).
• A Vector Space Model for Boolean Switching Networks, Proceedings of the International Workshop on Boolean Problems (IWSBP), September 17-19, 2014, pp. 1-21, (invited talk, link to abstract only, unpublished workshop proceedings).
• On the Relationship of Boolean Function Spectra and Circuit Output Probabilities, Proceedings of the International Workshop on Boolean Problems (IWSBP), September 17-19, 2014, pp. 33-39, (unpublished workshop proceedings, link to abstract only, with Micah Thornton).
• Mission Planning Analysis using Decision Diagrams (abstract only), Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design (RMW), May 24-25, 2013, pp. 61-65, (unpublished workshop proceedings, link to abstract only, with T.W. Manikas and F.R. Chang).
• Direct Reed-Muller Transform of Digital Logic Netlists, Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 25-26, 2011, pp. 11-20, (with J. Dworak).
• Toffoli Gate Cascade Generation Using ESOP Minimization and QMDD-based Swapping, Proceedings of the Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 23-24, 2009, pp. 63-72, (with J. Rice, K. Fazel, K. Kent).
• QMDD and Spectral Transformation of Binary and Multiple-Valued Functions, 8th International Workshop on Boolean Problems (IWBP), September 18-19, 2008, pp. 137-144, (with D.M. Miller).
• System-on-Chip Power Consumption Refinement and Analysis, Proceedings of the IEEE Dallas Workshop on Circuits and Systems, November 15-16, 2007, pp. 81-84, (with D. Feinstein and F. Kocan).
• Quantum Logic Circuit Simulation Based on the QMDD Data Structure, Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 16, 2007, pp. 99-105, (with D. Goodman, D.Y. Feinstein, and D.M. Miller).
• ESOP Transformation to Majority Gates for Quantum-dot Cellular Automata Logic Synthesis, Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 16, 2007, pp. 43-50, (with D.Y. Feinstein).
• Components of Disaster Tolerant Computing, International Workshop on Information Assurance, in conjunction with the IEEE International Performance Computing and Communications Conference, April 11-13, 2007, pp. 380-386, (with C.M. Lawler and M.A. Harper).
• Boolean Function Matching Using Walsh Spectral Decision Diagrams, Proceedings of the IEEE Dallas Workshop on Circuits and Systems, October 29-30, 2006, pp. 127-130, (with J. Moore, K. Fazel and D. M. Miller).
• Discrete Function KL Spectrum Computation over Symmetry Groups of Arbitrary Size, Proceedings of the International Symposium on Representations and Methodology of Future Computing Technologies (formerly, Reed-Muller Workshop, RMW05), September 5-6, 2005, pp. 110-113, (with Lun Li).
• A Standard Cell Implementation of a Phased Logic CPU, Workshop on Token Based Computing, Proceedings of the Workshop on Token Based Computing (ToBaCo), June 22, 2004, pp. 49-58, (with R. Reese and C. Traver).
• Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation, International Workshop on System-on-Chip for Real Time Applications (SOCRT), July 6-7, 2002, pp. 400-409, (with R. Drechsler, M. Kerttu and P. Lindgren).
• Low Power Optimization Technique for BDD Mapped Finite State Machines, International Workshop on Logic and Synthesis (IWLS), June 4-7, 2002, pp. 143-148, (with M. Kerttu, P. Lindgren and R. Drechsler).
• On Line Error Detection in a Carry Free Adder, International Workshop on Logic and Synthesis (IWLS), June 4-7, 2002, pp. 251-254, (with W. Towsend and P.K. Lala).
• Transformations Amongst the Walsh, Haar, Arithmetic and Reed-Muller Spectral Domains, International Workshop on Applications of the Reed-Muller Expansion in Circuit Design (RMW), August 10-11,  2001, pp. 215-225, (with D. M. Miller and R. Drechsler).
• Arithmetic Logic Circuits using Self-Timed Bit-Level Dataflow and Early Evaluation, International Workshop on Logic and Synthesis (IWLS), June 12-15,  2001, pp. 72-77, (with R. Reese and C. Traver).
• Low Power Optimization Technique for BDD Mapped Circuits, International Workshop on Logic Synthesis (IWLS), May 31-June 2, 2000, pp. 221-230, (with P. Lindgren and M. Kerttu).
• Probabilistic Equivalence Checking Using Partial Haar Spectral Diagrams, International Workshop on Applications of the Reed-Muller Expansion in Circuit Design (RMW), August 1999, pp. 123-132, (with R. Drechsler and W. Günther).
• Logic Synthesis Based on the Structure of an Ordered DD, International Workshop on Logic Synthesis (IWLS), July 1999, pp. 21-25, (with D. M. Wessels).
• Integration of CAD Tools and Structured Design Principles in an Undergraduate Computer Engineering Curriculum, Workshop on Computer Architecture Education, International Symposium on Computer Architecture (ISCA), June 1998, (with D. L. Andrews).
• Multiprocessor Resource Estimation Using a Stochastic Modeling Approach,  Symposium on Parallel and Distributed Processing, Workshop on Resource Estimation (SPDP), October 1996, (with D. L. Andrews and J. D. Bullard).
• Fast Reed-Muller Spectrum Computation Using Output Probabilities, Workshop on Applications of the Reed-Muller Expansion in Circuit Design (RMW), August 1995, pp. 281 - 287, (with V. S. S. Nair).
• Parity Function Detection and Realization Using a Small Set of Spectral Coefficients, IEEE/ACM International Workshop on Logic Synthesis (IWLS), May 1995, pp. 8-39 - 8-47, (with V. S. S. Nair).
• A Numerical Method for Reed-Muller Circuit Synthesis, Workshop on Applications of the Reed-Muller Expansion in Circuit Design (RMW), September 1993, pp. 69-74, (with V. S. S. Nair).

REGIONAL CONFERENCES

• Teaching a Laboratory Intensive Class in a Distance Education Mode, ASEE 2008 Midwest Section Conference, September 18-19, 2008, (with J. Moore and R.W. Skeith).
• Perl for Introductory Programming Classes, ASEE 2007 Midwest Section Conference, September 19-21, 2007, (with J. Moore and R.W. Skeith).
• Prefix Parallel Adder Virtual Implementation in Reversible Logic, IEEE Region 5 Technical Conference, April 20-22, 2007, pp. 74-80, (with D.Y. Feinstein and V.S.S. Nair).
• Multilevel Variable Length Shifter Design for an Iterated Shift-and-Add Product Operation , IEEE Region 5 Technical Conference, April 20-22, 2007, pp. 234-238, (with J. Moore and D.W. Matula).
• Encouraging Computer Engineering Students to Take the Fundamentals of Engineering (FE) Examination, ASEE 2006 Midwest Section Conference, September 15, 2006, on Proceedings CD-ROM, (with J. Moore and R. W. Skeith).
• An Undergraduate Course in Perl: An All Purpose Programming Language, ASEE Midwest Section Conference, September 14-16, 2005, on Proceedings CD-ROM, (with J. Moore and R.W. Skeith).
• A Modular and Specifications Oriented Digital Circuit Design Laboratory, ASEE Midwest Section Conference, September 29-October 1, 2004, (with J. Moore and R. W. Skeith).
• Research Results in Equivalence Checking, NSF Design, Service and Manufacturing Grantees and Research Conference, January 5-8, 2004, (with A. Mukherjee).
• UNIX Scripting and High-level Language Education Using an Emulator, ASEE Midwest Section Conference, September 2002, (with R. W. Skeith).
• Learning and Using UNIX on a MS Windows© Based Computer, Memphis Area Engineering and Sciences Conference (MAESC), May 10, 2002, p. 36, (with R. W. Skeith).
• Computation of Disjoint Cube Representations Using a Maximal Binate Variable Heuristic, IEEE Southeastern Symposium on System Theory, March 18-19, 2002, pp. 417-421, (with L. Shivakumaraiah).
• Partial Binary Decision Diagrams , IEEE Southeastern Symposium on System Theory, March 18-19, 2002, pp. 422-425, (with W. Towsend).
• Odd/Even Cube Covering for Minimizing ESOP Circuits, IEEE Southeastern Symposium on System Theory, March 2000, pp. 274-278, (with B. Q. Vu and R. Drechsler).
• Performance Evaluation of a Data Driven Architecture, 1996 Arkansas Computer Conference, March 1996, pp. 71-76.

ARTICLES, INTERVIEWS, OPINION PIECES AND MEDIA

• Forbes magazine, provided opinions and quotes to Forbes columnist Edward Segal regarding the widespread IT system failures due to the CrowdStrike software updates.  Published in an article “The Global IT Outage Provides Several Crisis Management Lessons” on July 19, 2024.
• TechXplore, Internet media published an article entitled "How to protect your personal info after AT&T's data breach" on July 15, 2024. Written by Irving Mejia-Hilario with quotes from Mitch Thornton.
• DFW Fox News 4, Interviewed for article "Tarrant County homowners' personal information released on the dark web," April 17, 2024, by reporter Dionne Anglin. Local news story aired at 5:30PM with quotes from Mitch Thornton.
• Dallas Morning News, Article entitled "How to protect personal info after AT&T's data breach," April 1, 2024. Written by Irving Mejia-Hilario with quotes from Mitch Thornton.
• North Texas eNews, Internet newspaper, article entitled "AI threats could make cyber threats harder to detect," February 28, 2024.
• YouTube.com, video of invited talk entitled "Cyber Autonomy Range" (talk begins at 45-minute timestamp) as part of the "Innovation forum" presented by Technology Ideation, LLC and delivered using the Polyplexus platform. The presentation was delivered on February 7, 2024.
• Viewpoint segment, hosted by Dennis Quaid, segment on PBS Newshour, (over 400 different local PBS TV stations), Quantum Cryptography, interview filmed at SMU in April 2023 with Anametric, Inc. founder Dr. Wil Oxford and AFRL Director, Dr. Michael Hayduk, segment aired in early 2024.
• Fox DFW channel 4, Good Day program at 9AM, appeared live for a segment entitled "AI could make cyber threats harder to detect," interviewed by Bryan Todd (video). A video clip of this segment and accompanying abstract was posted on the Yahoo news (news.yahoo.com), Microsoft news (msn.com) and Haystack TV (haystack.tv) websites on 1/24/24. The segment was also used in several Australian news sites including The Australian, The Daily Telegraph, NT News, Gold Coast Bulletin, Cairns Post, The Advertiser, Geelong Advertiser, and The Courier Mail. on January 26, 2024.
• SMU Press Release, AI Could Make Cyber Threats Harder to Detect, SMU News website, January 18, 2024.
• To PE or not to PE ... the story continues, IEEE-USA Insight (online public newsletter), January 22, 2024, (with S.F. Barrett and C.H.G. Wright).
• Fox Business Channel (FBC), U.S. national, December 14, 2023, 30-second commercial aired for Anametric, Inc. and mentioned collaboration with SMU researchers showing a research poster in the Darwin Deason Institute for Cyber Security. SMU has granted exclusive patent licenses to Anametric and IP was generated as a result of research at the Deason Institute.
• Spectrum News, December 11, 2023, appeared in story "Report: Chinese hackers targeted Texas power grid, Hawaii water utility, other infrastructure," by Lourdes Vazquez, 5PM news segment.
• ABC DFW channel 8 news, September 19, 2023, appeared in story "How SMU researchers are stopping cyberattacks," by Sydney Persing, 6PM news segment.
• NBC DFW channel 5 news, August 9, 2023, appeared in story "Dallas pays millions for ransomware expenses after May attack," by Ken Kalthoff, 6PM news segment.
• NBC DFW channel 5 news, May 5, 2023, appeared in story "City of Dallas Continues Battling Ransomware Attack for Third Day," by Ken Kalthoff, 4:30PM news segment and 6:00PM news segment. Reference and quote attribution appeared in on-line article "Dallas Ransomware Attack Continues for Third Day - NBC 5 Dallas-Fort Worth," at The Black Chronicle website.
• CBS DFW channel 11 news, December 7, 2022, interviewed regarding Governor Abbott's ban of TikTok on government issued devices, 5PM news segment, 6PM news segment
• SMU Press Release, SMU’s Deason Institute to partner with Goldman Sachs and Prairie View A&M for cyber security research, www.smu.edu, October 10, 2022, also related online articles at dallasweekly.com, pvamu.edu, rushhourtimes.com, cps-vo.org, jbhe.com.
• Raytheon Technlogies, Inc. Press Release, Raytheon Intelligence and Space Partners with Virginia Tech and Southern Methodist University on Artificial Intelligence and Machine Learning Research, February 23, 2021, also SMU press release, numerous web-based venues including: executivbiz.com, newsbreak.com, The Southwest Virginia Sun, The Dallas Express.
• CBS DFW channel 11 (web edition), SMU Lands $1M For Research Aimed At Cybersecurity, Quantum Computing Breakthroughs, December 8, 2020, from SMU press release. Also, numerous other online articles resulted including those posted at enterpriseai.news, insidequantumtechnology.com, newsbreak.com, sciencex.com, quantumzeitgeist.com, techtransfercentral.com, dallasinnovates.com, insidehpc.com, newlocker.com, December 2020 SMU Lyle Insider magazine, and others.
• Houston Chronicle (print edition), Hypersonic A&M, Opinion Editor, October 30, 2020, interviewed and quoted regarding quantum computing research in the U.S. and at SMU, hpcwire.com and others.
• Software Developed by SMU Stops Ransomware Attacks, Communications of the ACM (online edition), May 15, 2020.
• SMU Develops Anti-ransomware Program, The Daily Sentinel, Nacodoches, Texas daily newpaper, authored by AP, staff writer Josh Edwards, and SMU office of public relations, May 13, 2020.
• KRLD radio 1080AM, (Dallas), new sensor-based ransomware detection method from Deason Institute, Thornton interview, aired 6:52AM, May 14, 2020.
• Numerous on-line magazines ran sotries about the Deason Institute research results in ransomware detection. Including EurekaAlert! Science New-AAAS, newsbreak.com, Cyber Daily Report, CywareSocial, helpnetsecurity, DigitPol, phys.org-Security News, redes-zone (in Spanish), sciencebusiness.tech, sciencebusinesstechnews, scienmag.com-Technology, TechXplore, and others, May 13-15, 2020.
• KRLD radio 1080AM, (Dallas), cybersecurity concerns related to COVID19 pandemic interview, April 2, 2020.
• Dallas Morning News (print edition), The sound of things to come, Jordan Wilkerson, describes research about keyboard/smartphone snooping privacy, September 23, 2019.
• BBC radio, BBC World Service and two local UK BBC radio stations, interviewed by Oliver Conway and included in a radio piece about keyboard/smartphone snooping privacy, (audio recording at 11:33), additional similar stories on Dallas KRLD and KLIF radio stations
• Forbes, Forbes, Now hackers can use smartphones to secretly listen to what you're typing on your laptop keyboard, August 20, 2019, (authored by Jeb Su, Forbes correspondent with interview of M.A. Thornton).
• Dallas Morning News (online edition), SMU researchers find a new way to snoop with smartphones. But should you be worried?, August 13, 2019, (authored by Jordan Wilkerson, science reporter, also picked up by the Chicago Tribune, similar articles were written based on an SMU press release and appeared in several other newspapers, TV news, magazines, and online publications such as Yahoo! News).
• Communications of the ACM (online edition), SMU Researchers Find a New Way to Snoop with Smartphones. Should You Be Worried?, August 19, 2019.
• ABC 10 TV News story, Sacramento, CA, Hackers could hear your password when you type, (several other TV news channels ran this story including 12 News Phoenix, AZ;WTHR Pittsburgh, PA; WFMY Greensboro, NC; CBS19 Tyler, TX; WCNC, Charlotte, NC; WFAA, Dallas, TX; 9News, Sydney, Australia; many others.
• Dallas Morning News, Editorial, This could change everything: Bills would boost research into radically new way of computing, August 7, 2018, (authored by editorial board member Michael Lindenberger, including M.A. Thornton's research efforts in quantum computing at SMU).
• ME Today, Licensure and Certification: Two Different Forms of Professional Credentials, July 2014, (reprint of IEEE-USA Today's Engineer article in the mechanical engineering society ASME publication, ME Today).
• IEEE-USA Today's Engineer, Licensure and Certification: Two Different Forms of Professional Credentials, May 2014.
• PE The Magazine for Professional Engineers, The Path to Licensure, PE The Magazine for Professional Engineers, published by the NSPE, October 2012, p. 24-27, (authored by D. Boykin, with quotes from interview of M. A. Thornton).
• ASEE Peer, Faculty and Student Perceptions of Online Learning in Engineering Education, September 2012, (online reprint of peer-reviewed article in the 2012 ASEE Annual Conference, (with L. Kinney and M. Liu).
• IEEE-USA Today's Engineer, Intellectual Property Engineering Consulting and Professional Licensure, (October 2011).
• Dallas-Fort Worth KXAS, Channel 5, NBC affiliate, Internet Searches Reveal Bounty of Personal Information, local news interview aired on August 25, 2011, (reported by Kimberly King with interview of M.A. Thornton), video.
• Dallas-Fort Worth KTVT, Channel 11, CBS affiliate, State Fined Company Named in FBI Search Warrants, local news interview aired on August 23, 2011, (reported by Jack Fink with interview of M.A. Thornton), video.
• IEEE-USA Today's Engineer, When do Software Systems need to be Engineered?, July 2011, (with P.A. Laplante).
• IEEE-USA Today's Engineer, Should You Take the Computer Engineering PE Exam or the Electrical and Electronics Engineering PE Exam?, April 2011, (with A. Collins).
• IEEE-USA Today's Engineer, IEEE-USA and IEEE Computer Society Cooperate in New Professional Software Engineering Licensure Initiative (full version), January 2011, (with P.A. Laplante).
• IEEE-USA in ACTION, IEEE-USA and IEEE Computer Society Cooperate in New Professional Software Engineering Licensure Initiative (shortened version), December 2010, pp. 7-8, (with P. A. Laplante).
• IEEE-USA Today's Engineer, JPotential Change Slated for PE Educational Requirements, une 2010, (with S.F. Barrett and D.L. Whitman).
• IEEE-USA Today's Engineer, Why Should You Become a Licensed Professional Engineer?, February 2010.
• Dallas-Fort Worth KXAS, Channel 5, NBC affiliate, lSmart Meters can be Hacked: Security Experts, ocal news interview aired on Sept. 20 and 21, 2009, (anchored by Ken Kalthoff with interviews of M.A. Thornton and V.S. Nair), video.
• IEEE-USA Today's Engineer, Software Engineering PE Examination Development Approved, September 2009.
• IEEE-USA Today's Engineer, Why Computer Engineering Students Should Take the Fundamentals of Engineering Examination and How Professors can Help, June 2009, (with J. Moore and R. W. Skeith).
• PE The Magazine for Professional Engineers, Is It Time to License Software Engineers?, PE The Magazine for Professional Engineers, published by the NSPE, December 2007, p. 26-29, (authored by D. Boykin, with quotes from interview of M. A. Thornton).
• ChAPTER One Online Magazine, Student magazine of the AIChE, Criteria 2000 - The New Game - How Does it Play Out, September 1998, vol. 1, no. 1, (with R. E. Babcock and R. W. Skeith).

ABSTRACTS

• Time Series Clustering using Granger Causality to Identify Time Series Applicable to Forecasting Internal Waves in Lake and Marine Environments, American Geophysical Union - Fall Meeting (AGU), December 13-17, 2021, (with J. Sylvester, M. Lee, E.C. Larson, S. Aggarwal, M.J. Hornbach, M. Manga, and B. Miller).
• Embedded Systems Cyber Security at the Physical Layer, Information Systems and Computing Technology Networks (ISaCTN), (internal-only) Raytheon Technologies Conference, May 10, 2021.
• Model Checking for Security Analysis of Cyber-Physical Systems, International Conference on Data Intelligence and Security (ICDIS), June 28-30, 2019, (poster, with T.W. Manikas).
• An Open-source General Compiler for Quantum Computers, Free and Open Source Developers European Meeting (FOSDEM), February 3, 2019, (with K.N. Smith).
• Single Qubit Quantum Ring Oscillator and Applications for Storage and True Random Number Generation, Quantum Simulation & Computation Conference (QSC), February 12-16, 2018, (poster, with W.V. Oxford, D.L. MacFarlane, and T.P. LaFave, Jr.).
• Design and Implementation of a Photonic Quantum Storage Device, IBM Think Q Conference, December 6-8, 2017, (poster, with William V. Oxford, James S. Gable, Duncan L. MacFarlane, and Timothy P. LaFave, Jr.).
• Single Photon Quantum State Oscillator, poster, NIST Single Photon Worksop (SPW), July 31 - August 4, 2017,p. 140, (with D.L. MacFarlane, T.P. LaFave, Jr., and W.V. Oxford).
• Sample Size Calculations using Techniques from Power Analysis, poster, ASA Conference on Statistical Practice (CSP), February 20, 2016, p. 27, (with M.A. Thornton, J. Rendon, and G. Pham).
• Use of Hamming Weights Instead of Uniform Distributions to Analyze a Set of Strings for Randomness, poster, ASA Conference on Statistical Practice (CSP), February 20, 2016, p. 27, (with J. Rendon, M.A. Thornton, and G. Pham).
• Setting the Stage for CE2016: A Revised Body of Knowledge, Frontiers in Education Conference (FIE), Oct. 22-25, 2014, (workshop co-facilitator, with E. Durant, J. Impagliazzo, S. Conroy, R.B. Reese, H. Lam, and V. Nelson).
• Computer Engineering Curriculum Guidelines Pre-Conference Workshop, Frontiers in Education Conference, October 23-26, 2013, p. 1, (workshop co-facilitator, with E. Durant, S. Conroy, J. Impagliazzo, A. McGettrick, and T. Wilson).
• Special Session: CE2004 Revisions (Computer Engineering Curriculum Guidelines) Special Session, Frontiers in Education Conference (FIE), October 3-6, 2012, (with E.Durant, S. Conroy, J. Impagliazzo, A. McGettrick, and T. Wilson).
• Computer Engineering Review Task Force Report, Panel Presentation, ACM SIGCSE Technical Symposium on Computer Science Education (SIGCSE), February 29-March 3, 2012, pp. 401-402, (panelist, with J. Impagliazzo, moderator, S. Conroy, E. Durant, A. McGettrick, and T. Wilson).
• Axiomatic Analysis and Cyber Threat Tree Models for the Development of Large-Scale Disaster-Tolerant Information Security Systems, Raytheon Information Systems and Computing Technology Network Symposium (ISaCTN), April 21, 2010, (with T. Manikas).
• Advances in Quantum Computing Fault Tolerance and Testing, IEEE High Assurance Systems Engineering Symposium (HASE), November 14-16, 2007, pp. 369-370, (with D. Y. Feinstein and V.S.S. Nair).
• A Second Undergraduate Course in Digital Logic Design: The Datapath+Controller-based Approach, ASEE 2003 Southeastern Section Conference, April 2003, (with A. S. Collins).
• UNIX and High-level Language Education Using Windows Operating Systems, ASEE 2001 Southeastern Section Meeting, April 2001, (with R. W. Skeith).
• Binary Decision Diagram Visualization: A Research Experience for Undergraduates, ASEE Thirty-Fourth Midwest Section Conference, April 1999, (with R. W. Skeith, S. M. Karp, J. N. Taylor).
• Integration of CAD Tools and Structured Design Principles in an Undergraduate CE Curriculum, IEEE Computer Architecture Technical Committee Newsletter, February 1999, pp.8-9, (with D. L. Andrews).
• Assessment Analysis in Criteria 2000, ASEE Thirty-Third Midwest Section Conference, April 1998, (with R. W. Skeith).
• Integration of Hardware Description Languages into an Undergraduate Design Laboratory Course, ASEE Thirty-First Midwest Section Conference, April 1996.

TECHNICAL REPORTS

• Automated Quantum Circuit Generation for Computing Inverse Hash Functions, arXiv.2404.17142 [quant-ph], April 26, 2024, (with E.R. Henderson, J.M. Henderson and W.V. Oxford).
• Designing a Photonic Physically Unclonable Function Having Resilience to Machine Learning Attacks, arXiv:2404.02440 [cs.CR], April 3, 2024, (with E.R. Henderson, J.M. Henderson, H. Shahoei, W.V. Oxford, E.C. Larson and D.L. MacFarlane).
• A Photonic Physically Unclonable Function’s Resilience to Multiple-Valued Machine Learning Attacks, arXiv:2403.01299 [cs.CR], March 5, 2024, (with J.M. Henderson, E.R. Henderson, C.A. Harper, H. Shahoei, W.V. Oxford, E.C. Larson and D.L. MacFarlane).
• Automated Synthesis of Quantum Subcircuits, arXiv:2309.01028 [quant-ph], September 2, 2023, (with E.R. Henderson, J.M. Henderson, A. Sinha, E.C. Larson and D.M. Miller).
• CNN-Assisted Steganography - Integrating Machine Learning with Established Steganographic Techniques, arXiv:2304.12503v1 [cs.CR], April 25, 2023, (with A. Havard, T.W. Manikas andE.C. Larson).
• Automated Quantum Oracle Synthesis with a Minimal Number of Qubits, arXiv:2304.03829 [quant-ph], April 7, 2023, (with J.M. Henderson, E.R. Henderson, A. Sinha and E.C. Larson).
• A Programmable True Random Number Generator using Commercial Quantum Computers, arXiv:2304.03830 [quant-ph], April 7, 2023, (with A. Sinha, E.R. Henderson, J.M. Henderson and E.C. Larson).
• Cyber Autonomy Range (brochure), Darwin Deason Institute for Cyber Security, Southern Methodist University, February 2023.
• Automatic Modulation Classification with Deep Neural Networks, arXiv:2301.11773v1 [cs.LG], January 27, 2023, (with C.A. Harper and E.C. Larson).
• Automated Quantum Memory Compilation with Improved Dynamic Range, arXiv:2211.09860v1 [quant-ph], November 17, 2022, (with A. Sinha, E.R. Henderson and J.M. Henderson).
• Entanglement in Higher-Radix Quantum Systems, arXiv:1906.00491v1 [quant.ph], June 2, 2019, (with K.N. Smith).
• Using ZDDs in the Mapping of Quantum Circuits, arXiv:1901.02406v3 [quant-ph], May 1, 2020, (with K.N. Smith, M. Soeken, B. Schmitt and G. De Michelli).
• An Overview of Placement and Routing Algorithms for PCB, VLSI, and MCM Designs with a Proposal for a New MCM Routing Algorithm, Technical Report, Dept. of Computer Systems Engineering, University of Arkansas, Fayetteville, Arkansas, 1996, (written by C. N. Frisbee, directed by M. A. Thornton).
• Iterative Combinational Logic Synthesis Techniques Using Spectral Data, Technical Report, Southern Methodist University, CSE-9208, 1992 (with V. S. S. Nair).
• Applications and Efficient Computation of Spectral Coefficients for Digital Logic, Technical Report, Southern Methodist University, CSE-9413, 1994, (with V. S. S. Nair).
• Boolean Function Spectrum Computation Using a Structural Representation, Technical Report, Southern Methodist University, CSE-9440, 1994, (with V. S. S. Nair).
• Reed-Muller Circuit Synthesis Using Numerical Methods, Technical Report, Southern Methodist University, CSE-9319, 1993, (with V. S. S. Nair).

DISSERTATIONS/THESES

• Real-time Detection and Suppression of Malicious Attacks using Machine Learning and Processor Core Events, Ph.D. dissertation, Dept. of Computer Science, Southern Methodist University, May 13, 2023, (written by Rob Oshana, directed by M.A. Thornton).
• Data Leakage in Isolated Virtualized Enterprise Computing Systems, M.S. thesis, Dept. of Computer Science, Southern Methodist University, May 13, 2023, (written by Zech Wolf, directed by M.A. Thornton).
• Enhanced Security Utilizing Side Channel Data Analysis, Ph.D. dissertation, Dept. of Electrical and Computer Engineering, Southern Methodist University, December 18, 2021, (written by Michael A. Taylor, directed by M.A. Thornton).
• Technology-dependent Quantum Logic Synthesis and Compilation, Ph.D. dissertation, Dept. of Electrical and Computer Engineering, Southern Methodist University, December 21, 2019, (written by Kaitlin N. Smith, directed by M.A. Thornton).
• Implementation of Switching Function Circuit Models as Vector Space Transformations, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, December 16, 2017, (written by David Kebo Houngninou, directed by M.A. Thornton).
• Ransomware Detection using Machine Learning and Physical Sensor Data, M.S.C.p.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, December 16, 2017, (written by Michael A. Taylor, directed by M.A. Thornton).
• Demographic Group Prediction Based on Smart Device User Recognition Gestures, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, April 26, 2017, (written by Adel Alharbi, directed by M.A. Thornton).
• Automated Detection of Submerged Navigational Obstructions in Freshwater Impoundments with Hull Mounted Sidescan Sonar, M.S.C.p.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, July 8, 2015, (written by P. Morris, directed by M.A. Thornton).
• Specialized Multiplier Circuits, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, December 4, 2014, (written by J. Moore, directed by M.A. Thornton).
• A Fixed-point Digit-Serial Squaring Algorithm using an Arbitrary Number System, M.S.C.p.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, August 3, 2012, (written by Saurabh Gupta, directed by M.A. Thornton).
• A Global Multiple-Valued Clock Approach for High-Performance Multi-Phase Clock Integrated Circuits, M.S.C.p.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, December 2, 2011, (written by Rohit Menon, directed by M.A. Thornton).
• A Novel Approach to Business Process Design in a Regulated Industry, Ph.D. dissertation, Dept. of Applied Science, Southern Methodist University, April 21, 2011, (written by Diana Easton, directed by M.A. Thornton).
• Securing Unfamiliar Entry Points Against Faulty User Authentication Via Electromagnetic Side Channel Attacks, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 27, 2010, (written by John J. Howard, directed by M.A. Thornton).
• Design and Validation of Quaternary Arithmetic Circuits, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, December 4, 2009, (written by Satyendra Datla, directed by M.A. Thornton).
• Computer-Aided-Design Methods for Emerging Quantum Computing Techniques, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, April 18, 2008, (written by David Feinstein, directed by M.A. Thornton).
• Quantum Logic Implementation of Unary Arithmetic Operations with Inheritance, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 24, 2008, (written by Laura Spenner, directed by M.A. Thornton).
• Hardware Acceleration of Software Library String Functions, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, December 2007, (written by P. Kulkarni, directed by M.A. Thornton).
• An Automated Tool for HDL and Configuration File Generation from UML System Descriptions, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, June 2007, (written by K. Hawkins, directed by M.A. Thornton).
• A Quantum Logic Simulator Based on Decision Diagrams, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 2007, (written by D. Goodman, directed by M.A. Thornton).
• Integrated Techniques for the Formal Verification and Validation of Digital Systems, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, May 2006, (written by Lun Li, directed by M. A. Thornton)
• Crosstalk Delay Analysis in Very Deep Submicron VLSI Circuits, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 2004, (written by Satyendra Datla, directed by M. A. Thornton).
• Performance Enhancement Techniques for Phased Logic Circuits, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 2004, (written by Kenneth B. Fazel, directed by M. A. Thornton).
• Discrete Function Representations utilizing Decision Diagrams and Spectral Techniques, M.S.E.E thesis, Dept. of Electrical and Computer Engineering, Mississippi State University, August 2002, (written by W.J. Townsend, directed by M. A. Thornton).
• Application of Decision Diagrams for Information Storage and Retrieval, M.S.E.E. thesis, Dept. of Electrical and Computer Engineering, Mississippi State University, May 2002, (written by Vivek Komarigiri, directed by M. A. Thornton).
• ESOP Circuit Minimization Based on the Function On-Set, M.S.E.E. thesis, Dept. of Electrical and Computer Engineering, Mississippi State University, August 2000, (written by Likai Chai, directed by M. A. Thornton).
• A Split Data Cache Organization Based on Run-time Data Locality Estimation, Ph.D. dissertation, Dept. of Computer Science and Computer Engineering, University of Arkansas, May 2000, (written by Quazi Galib Samdani, directed by M. A. Thornton).
• An FPGA Approach for SNR Estimation Using Phase-Only Data, M. S. C. S. E. Thesis, Dept. of Computer Systems Engineering, University of Arkansas, August 1999, (written by Pramodini Arramreddy, directed by M. A. Thornton).
• A BDD Variable Reordering Heuristic Based on Output Probability Periodicity, M. S. C. S. E. Thesis, Dept. of Computer Systems Engineering, University of Arkansas, Fayetteville, Arkansas, December 1998, (written by Joshua P. Williams, directed by M. A. Thornton).
• Probability Based Variable Ordering and Reordering Heuristics for Decision Diagrams, M. S. C. S. E. Thesis, Dept. of Computer Systems Engineering, University of Arkansas, Fayetteville, Arkansas, August 1997, (written by Roger P. Moore, directed by M. A. Thornton).
• Implementation of Compiler, Viewer, and Parallelism Analysis Software for the IF1 Language, M. S. E. Thesis, Dept. of Computer Systems Engineering, University of Arkansas, Fayetteville, Arkansas, December 1996, (written by Suwanto, directed by M. A. Thornton).
• Spectral Based Numerical Methods for Combinational Logic Synthesis, Ph.D. dissertation, Department of Computer Science and Engineering, Southern Methodist University, August 4, 1995.