JOURNAL ARTICLES
 Higherradix Chrestenson Gates for Optical Quantum Computation, Journal of Applied Logics, vol. 5, iss. 9, pp. 17811798, December 2018, (with K.N. Smith, T.P. LaFave, Jr., and D.L. MacFarlane).
 A FixedPoint Squaring Algorithm Using an Implicit Radix Number System, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, iss. 1, pp. 3443, March 2016, (prepublished February 2016, IEEEXplore, with S.D. Gupta).
 QMDDs: Efficient Quantum Function Representation and Manipulation, IEEE Transactions on ComputerAided Design, vol. 35, no. 1, pp. 8699, January 2016, (prepublished July 21, 2015, IEEEXplore.ieee.org prepublication version, with P. Niemann, R. Wille, D.M. Miller, and R. Drechsler).
 Simulation and Implication using a Transfer Function Model for Switching Logic, IEEE Transactions on Computers, vol. 64, no. 12, pp. 35803590, December 2015, (prepublished Feb. 6, 2015, IEEEXplore.ieee.org prepublication version).
 Quantum MultipleValued Decision Diagram: The Case of Skipped Variables, Journal of MultipleValued Logic and Soft Computing, vol. 24, 2015, no. 14, pp. 93108, (with D.Y. Feinstein).
 Modeling System Threat Probabilities Using MixedRadix MultipleValued Logic Decision Diagrams, Journal of MultipleValued Logic and Soft Computing, vol. 24, 2015, no. 14, pp. 135149, (with T. Manikas, and D.Y. Feinstein).
 On Optimizations of EdgeValued MDDs for Fast Analysis of MultiState Systems, IEICE Trans. Inf. & Syst., vol. E97D, no. 9, September 2014, pp. 22342242, (with S. Nagayama, T. Sasao, J.T. Butler, and T.W. Manikas).
 Clock Distribution Area Reduction Using a MultipleValued Clocking Approach, Journal of MultipleValued Logic and Soft Computing, vol. 22, no. 12, 2014, pp. 2139, (with R.P. Menon).
 A Principles and Practices Exam Specification to Support Software Engineering Licensure in the United States of America, Software Quality Professional, December 2012, vol. 15, iss. 1, pp. 415, (with P.A. Laplante and B. Kalinowski).
 Professional Licensure for Software Engineers: An Update, IEEE Computing in Science and Engineering, IEEE Computer Society Press and American Institute of Physics, SeptemberOctober 2012, vol. 14, iss. 5, pp. 8687, IEEEXplore.ieee.org version.
 Reversible Logic Synthesis Based on Decision Diagram Variable Ordering, Journal of MultipleValued Logic and Soft Computing, vol. 19, no. 4, 2012, pp. 325339, (with D.Y. Feinstein).
 Business Process Development Through the Use of a Modified Axiomatic Design Methodology, Journal of International Business Management & Research, vol. 2, issue 4, May 2011, (with D. Easton).
 An Axiomatic Approach for LargeScale DisasterTolerant Systems Modeling, IIIS Journal of Systematics, Cybernetics and Informatics, vol. 9, no. 1, 2011, pp. 8993, (with T. Manikas, L.L. Spenner, P.D. Krier, S. Nair, and S.A. Szygenda).
 To PE or not to PE ... The Sequel, IEEE Computing in Science and Engineering, IEEE Computer Society Press and American Institute of Physics, July/August 2010, vol. 12, no. 4, pp. 6265, (with Steven F. Barrett), IEEEXplore.ieee.org version.
 Minimization of Quantum MultipleValued Decision Diagrams using Data Structure Metrics, Journal of MultipleValued Logic and Soft Computing, vol. 15, no. 4, 2009, pp. 361377, (with D.Y. Feinstein and D.M. Miller).
 A Redundant Signed Binary Addition Based DigitaltoFrequency Converter, IEE Electronics Letters, vol. 45, no. 2, pp. 824826, July 2009, (with W. Chen and P. Gui).
 A Discrete Logarithm Number System for Integer Arithmetic Modulo 2^{k}: Algorithms and Lookup Structures, IEEE Transactions on Computers, vol. 58, no. 2, Feb. 2009, pp. 163174, (with A. FitFlorea, L. Li, and D.W. Matula), IEEEXplore.ieee.org version.
 A Methodology for Disaster Tolerance Utilizing the Concepts of Axiomatic Design, IIIS Journal of Systemics, Cybernetics and Informatics, vol. 6, no. 4, 2008, (with D. Easton, V.S.S. Nair, and S.A. Szygenda).
 Components of Disaster Tolerant Computing: Analysis of Disaster Recovery, IT Application Downtime & Executve Visibility, International Journal of Business Information Systems,vol. 3, no. 3, 2008, pp. 317331, (with C.M. Lawler, M.A. Harper, and S.A. Szygenda).
 QMDD Minimization using Sifting for Variable Reordering, Journal of MultipleValued Logic and Soft Computing, vol. 13, no. 46, 2007, pp. 537552, (with D.M. Miller and D.Y. Feinstein).
 Integrated Design Validation: Combining Simulation and Formal Verification in Integrated Circuit Design, IIIS Journal of Systemics, Cybernetics and Informatics, vol. 4, no. 2, 2006, (with L. Li and S. Szygenda).
 A CoarseGrain Phased Logic CPU, IEEE Transactions on Computers, vol. 54, no. 7, July 2005, pp. 788799, (with R. B. Reese and C. Traver).
 Early Evaluation for Performance Enhancement in Phased Logic, IEEE Transactions on Computer Aided Design, (vol. 24, no. 4, pp. 532550, April 2005, (with R. B. Reese, C. Traver, and D. Hemmendinger).
 Additive Bitserial Algorithm for the Discrete Logarithm Modulo 2^{k}, IEE Electronics Letters, vol. 41, no. 2, pp. 5759, January 2005, (with A. FitFlorea and D.W. Matula).
 Additionbased Exponentiation Modulo 2^{k}, IEE Electronics Letters, vol. 41, no. 2, pp. 5657, January 2005, ( with A. FitFlorea and D.W. Matula).
 Computation of Discrete Function Chrestenson Spectrum Using Cayley Color Graphs, Journal of MultipleValued Logic and Soft Computing, vol. 10, no. 2, 2004, pp. 189202, (with D. Michael Miller).
 Mixedradix MVL Function Spectral and Decision Diagram Representation, Automation and Remote Control, vol. 65, issue 6, June 2004, pp. 10071017, (invited paper, in English and Russian).
 A Twophase Micropipeline Control Wrapper with Early Evaluation, IEE Electronics Letters, vol. 40, no. 6, March 2004, pp. 365366, (with R. B. Reese and C. Traver).
 A Fast Twophase Micropipeline Control Wrapper for Standard Cell Implementation, IEE Electronics Letters, vol. 40, no. 4, February 2004, pp. 1920, (with R. B. Reese and Cherrice Traver).
 Performance Evaluation of a Parallel Decoupled Data Driven Multiprocessor, Parallel Processing Letters, vol. 13, no. 3, September 2003, pp. 497507.
 A Signed Binary Addition Circuit Based on an Alternative Class of Addition Tables, Computers & Electrical Engineering, vol. 29, no. 2, March 2003, pp. 303315.
 Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation, Canadian Journal of Electrical and Computer Engineering, vol. 27, no. 4, October 2002, pp. 159164, (invited paper, with R. Drechsler, M. Kerttu and P. Lindgren).
 Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs, VLSI Design, vol. 14, no. 1, February 2002, pp. 5364, (with R. Drechsler and W. Günther).
 Boolean Function Representation and Spectral Characterization Using AND/OR Graphs, Integration, the VLSI Journal, vol. 29, September 2000, pp. 101116, (with A. Žužek and R. Drechsler).
 Behavioral Synthesis of Combinational Logic Using Spectral Based Heuristics, ACM Transactions on Design Automation of Electronic Systems, vol. 4, no. 2, April 1999, pp. 219230, (with V. S. S. Nair).
 Resource Estimation for Parallel Architectures with Distributed Processor/Memory Nodes, Journal of Computing and Information Technology, vol. 6, no. 4, December 1998, pp. 359371 (with D. L. Andrews).
 Signed Binary Addition Circuitry with Inherent Even Parity Outputs, IEEE Transactions on Computers, vol. 46, no. 7, July 1997, pp. 811816.
 BDD Based Spectral Approach for ReedMuller Circuit Realisation, IEE ProceedingsComputers and Digital Techniques, vol. 193, issue 2, March 1996, pp. 145150, (with V. S. S. Nair).
 Efficient Calculation of Spectral Coefficients and their Application, IEEE Transactions on Computer Aided Design, vol. 14, no. 11., November 1995, pp. 13281341, (with V. S. S. Nair).
 Efficient Calculation of Spectral Coefficients of Combinational Circuits, Digital Signal Processing: A Review Journal, October 1994, pp. 245254, (with V. S. S. Nair).
BOOKS
 Modeling Digital Switching Circuits with Linear Algebra, Morgan & Claypool Publishers, San Rafael, California, ISBN 9781627052337 (hardcopy), ISBN 9781627052344 (eBook), April 2014.
 Digital System Verification: A Combined Formal Methods and Simulation Framework, Morgan & Claypool Publishers, San Rafael, California, ISBN 9781608451784 (hardcopy), ISBN 9781608451791 (eBook), February 2010, (with L. Li).
 MultipleValued Logic Concepts and Representations, Morgan & Claypool Publishers, San Rafael, California, ISBN 101598291904 (hardcopy), 101598291912 (eBook), January 2008, (with D. M. Miller).
 Introduction to Logic Synthesis Using Verilog HDL, Morgan & Claypool Publishers, San Rafael, California, ISBN 101598291068 (hardcopy), ISBN 101598291076 (eBook), November 2006, (with R. B. Reese).
 Spectral Techniques in VLSI CAD, Kluwer Academic Publishers, Boston, Massachusetts, ISBN 0792374339, July 2001 (with R. Drechsler and D. M. Miller).
BOOK CHAPTERS AND ENCYCLOPEDIA ARTICLES
 Foreward, Further Improvements in the Boolean Domain, Cambridge Scholars Publishing, Cambridge, UK, Bernd Steinbach, Editor, (to appear).
 A Vector Space Method for Boolean Networks, Chapter 1, Section 1.1, in Problems and New Solutions in the Boolean Domain, Cambridge Scholars Publishing, Cambridge, UK, Bernd Steinbach, Editor, 2015, ISBN 139781443889476; 101443889474, pp. 350, January 5, 2016.
 Boolean Function Spectra and Circuit Probabilities, Chapter 4, Section 4.1, in Problems and New Solutions in the Boolean Domain, Cambridge Scholars Publishing, Cambridge, UK, Bernd Steinbach, Editor, 2015, ISBN 139781443889476; 101443889474, January 5, 2016, pp. 269286, (with Micah A. Thornton).
 The Best of IEEEUSA Insight: On Licensing Software Engineers, Article Reprints in Parts I, II, and III, IEEEUSA Publishing, Washington D.C., compiled by P. A. Laplante, Georgia C Stelluto, editor, 2015.
 Quantum Computing Approach for Alignmentfree Sequence Search and Classification, Chapter 17 in Multidisciplinary Computational Intelligence Techniques: Applications in Business, Engineering, and Medicine, S. Ali, N. Abbadeni, and M. Batouche, Editors, IGIGlobal Press, pp. 279300, May 2012, ISBN 9781466618305 (hardcopy), ISBN 9781466618312 (eBook), (with R. Kotamarti and M.H. Dunham).
 Licensing Professional Software Engineers in the United States of America, Article in the Encyclopedia of Software Engineering, Taylor & Francis, New York, DOI: 10.1081/EESE, ISBN:1420059777; eISBN: 1420059785, Published online: April 24, 2012, pp. 18, (with P. A. Laplante).
 Keystroke Dynamics, Article in the Encyclopedia of Cryptography and Security, 2nd edition, H. C. A. van Tilborg and S. Jajodia, Editors, Springer Publishers, pp. 688691, November 2011, ISBN 9781441959058.
 Multiprocessor Memory Resource Estimation, Chapter 10 in Parallel and Distributed Systems: Architectures, Tools and Algorithms, Jose Aguilar, Editor, IIIS Publishers, ISBN 9800759565, July 2001 (with D. L. Andrews).
 ComputerAided Engineering and Design, Chapter 8 in ADVANCED ELECTRONIC PACKAGING: With Emphasis on MultiChip Modules, W. D. Brown, Editor, IEEE Press, Piscataway, New Jersey, ISBN 0780347005, 1999, (with D. L. Andrews, J. M. Conrad and M. D. Glover).
 Microprocessor Systems, Article in the Encyclopedia of Life Support Systems, EOLSS Publishers Co. Ltd., March 2003.
PATENTS
 FixedPoint Digit Serial Squaring Algorithm, U.S. Patent 9,684,489, June 20, 2017, Filed August 31, 2012, (Coinventor with S. Gupta).
 Method for Subject Classification Using a Pattern Recognition Input Device, U.S. Patent 9,329,699, May 3, 2016, Application No. 13/279,279, Filed October 22, 2011, Claiming priority from provisional patent application 61/405,988, filed October 22, 2010, (Coinventor with J.D. Allen and J.J. Howard).
 Single Clock Distribution Network for MultiPhase Clock Integrated Circuits, U.S. Patent 8,847,625, September 30, 2014, Application No. 13/769,313, Filed 16 February, 2013, Claiming priority from provisional patent application 61/599,598, filed 16 February 2012, (Coinventor with R. Menon).
 Determining a Table Output of a Table Representing a Hierarchical Tree for an Integer Valued Function, U.S. Patent 7,962,537, June 14, 2011, Filed June 26, 2007, (Coinventor with D.W. Matula, A. FitFlorea, and L. Li).
 Method for Early Evaluation in Micropipeline Processors, U.S. Patent 7,043,710, May 9, 2006, Filed February 10, 2004, (Coinventor with R.B. Reese).
 Systems and Methods for Quantum Coherence Preservation of Qubits, U.S. Patent Application, No. 15/832,285, filed December 5, 2017, Pub. No. US2018/0157986A1, Pub. Date June 7, 2018, claiming priority from: Bell State Oscillator and Applications for Same, U.S. Provisional Patent 62/430,501, filed December 6, 2016, (Coinventor with W.V. Oxford, D.L. MacFarlane, and T.P. LaFave, Jr.).
 Systems and Methods for Preservation of Qubits, U.S. Patent Application No. 15/965,286, filed April 27, 2018, claiming priority from: Quantum State Oscillators and Methods for Operation and Construction of Same, U.S. Provisional Patent No. 62/491,815, filed April 28, 2017, (Coinventor with D.L. MacFarlane, T.P. LaFave, Jr., and W.V. Oxford).
 Detecting Malicious Software using Sensors, U.S. Patent Application, No. 15/812,663, filed November 14, 2017, (Coinventor with M.A. Taylor and K.N. Smith).
 Systems and Methods for Implementing Photonic Quantum Storage, U.S. Provisional Patent, Application No. 62/613,262, filed January 3, 2018, (Coinventor with W.V Oxford, D.L. MacFarlane, T.P. LaFave, Jr., and J.S. Gable).
 Method and System for Increasing the Effective Sample Rate of a Sampled Signal, U.S. Patent Pending, (Coinventor with E.C. Larson, E. Gabrielsen, and I. Johnson).
 Method and System for Constructing a Multisource Entropy Extractorbased Quantum Photonic TRNG, U.S. Provisional Patent, filed March 15, 2019, (Coinventor with D.L. MacFarlane and W.V. Oxford).
NATIONAL/INTERNATIONAL CONFERENCES
 A Quantum Computational Compiler and Design Tool for Technologyspecific Targets, IEEE International Symposium on Computer Architecture (ISCA),June 2226, 2019, (to appear, with K.N. Smith).
 Entanglement in HigherRadix Quantum Systems, IEEE International Symposium on MultipleValued Logic (ISMVL), May 2123, 2019, pp. 162167, (to appear, with K.N. Smith).
 Task Value Calculus: Multiobjective Tradeoff Analysis using Multiplevalued Decision Diagrams, IEEE International Symposium on MultipleValued Logic (ISMVL), May 2123, 2019, pp. 162167, (to appear, with T. Giallanza, E. Gabrielsen, M.A. Taylor, and E.C. Larson).
 Quantum Photonic TRNG with Dual Extractor, International Conference on Networked Systems/Workshop on Quantum Technology and Optimization Problems (NetSys/QTOP), SpringerVerlag LNCS 11413, March 1821, 2019, pp. 171182, (with D.L. MacFarlane).
 A 2.56 Gbps Asynchronous Serial Transceiver with Embedded 80 Mbps Secondary Data Transmission Capability in 65nm CMOS, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 1012, 2018, pp. 360  363, (with X. Wang, T. Liu, S. Guo, and P. Gui).
 MultipleValued Random Digit Extraction, IEEE International Symposium on MultipleValued Logic (ISMVL), May 1618, 2018, pp. 162167, (with Micah A. Thornton).
 A Radix4 Chrestenson Gate for Optical Quantum Computation, IEEE International Symposium on MultipleValued Logic (ISMVL), May 1618, 2018, pp. 260265, (with K.N. Smith, T.P. LaFave, Jr., and D. MacFarlane).
 SensorBased Ransomware Detection, Future Technologies Conference (FTC), November 2930, 2017, pp. 794801, (with M.A. Taylor and K.N. Smith).
 Simulation of Switching Circuits using Transfer Functions, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 69, 2017, pp. 511514, (with D.K. Houngninou).
 Automated Markovchain Based Analysis for Large State Spaces, IEEE International Systems Conference (SYSCON), April 2427, 2017, pp. 306313, (with K.N. Smith, M.A. Taylor, A.A. Carroll, and T.W. Manikas).
 Demographic Group Prediction Based on Smart Device User Recognition Gestures, IEEE International Conference on Machine Learning and Applications (ICMLA), pp. 100107, December 1820, 2016, (with A. Alharbi).
 Implementation of Switching Circuit Models as Transfer Functions, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 21672170, May 2225, 2016, (with D.K. Houngninou).
 Reliability Block Diagram Extensions for NonParametric Probabilistic Analysis, IEEE International Systems Conference (SYSCON), pp. 927932, April 1821, 2016, (with P.C. Davis and T.W. Manikas).
 Demographic Group Classification of Smart Device Users, IEEE International Conference on Machine Learning and Applications (ICMLA), pp. 481486, December 911, 2015, (with A. Alharbi).
 An Improved Methodology for System Threat Analysis using MultipleValued Logic and Conditional Probabilities, Society for Design and Process Science (SDPS), November 15, 2015, (with T.W. Manikas and S. Nagayama).
 A MultipleValued Logic Synthesis Tool for Optical Computing Elements, IEEE Dallas Circuits and Systems Conference (DCAS), pp. 14, paper 382.3, October 1213, 2015, (with K.N. Smith).
 Edge Reduction for EVMDDs to Speed Up Analysis of MultiState Systems, IEEE International Symposium on MultipleValued Logic (ISMVL), May 1820, 2015, pp. 170175, (with S. Nagayama, T. Sasao, J.T. Butler, and T.W. Manikas).
 System Probability Distribution Modeling using MDDs, IEEE International Symposium on MultipleValued Logic (ISMVL), May 1921, 2014, pp. 196201, (with T.W. Manikas, S.A. Szygenda, and S. Nagayama).
 Analysis Methods of MultiState Systems Partially having Dependent Components using MultipleValued Decision Diagrams, IEEE International Symposium on MultipleValued Logic (ISMVL), May 1921, 2014, pp. 190195, (with S. Nagayama, T. Sasao, J.T. Butler, and T.W. Manikas).
 Embedded and Realtime Systems Classes in Traditional and Distance Format, Frontiers in Education Conference (FIE), October 2326, 2013, pp. 13791385, (with T.W. Manikas and P.A. Laplante).
 Low Power FloatingPoint Multiplication and Squaring Units with Shared Circuitry, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 4, 2013, pp. 13951398, (with J. Moore and D.W. Matula).
 A Transfer Function Model for Ternary Switching Logic Circuits, IEEE International Symposium on MultipleValued Logic (ISMVL), May 2425, 2013, pp. 103108.
 Ternary Logic Network Justification Using Transfer Matrices, IEEE International Symposium on MultipleValued Logic (ISMVL), May 2425, 2013, pp. 310315, (with J. Dworak).
 Spectral Response of Ternary Logic Netlists, IEEE International Symposium on MultipleValued Logic (ISMVL), May 2425, 2013, pp. 109116, (with T.W. Manikas).
 Using the Asynchronous Paradigm for Reversible Sequential Circuit Implementation, IEEE International Symposium on MultipleValued Logic (ISMVL), May 1416, 2012, pp. 305310, (with D.Y. Feinstein).
 Global Multiplevalued Clock Approach for Highperformance Multiphase Clock Integrated Circuits, IEEE International Symposium on MultipleValued Logic (ISMVL), May 1416, 2012, pp. 1924, (with R.P. Menon).
 Modeling Medical System Threats with Conditional Probabilities using Multiplevalued Logic Decision Diagrams, IEEE International Symposium on MultipleValued Logic (ISMVL), May 1416, 2012, pp. 244249, (with T.W. Manikas and D.Y. Feinstein).
 UncleAn RTL Approach to Asynchronous Design, IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 79, 2012, pp. 6572, (with R.B. Reese and S.A. Smith).
 Faculty and Student Perceptions of Online Learning in Engineering Education, ASEE Annual Conference, June 1013, 2012, (with L. Kinney and M. Liu).
 On the Skipped Variables of Quantum Multiplevalued Decision Diagrams, IEEE International Symposium on MultipleValued Logic (ISMVL), May 2325, 2011, pp. 164168, (with D.Y. Feinstein).
 Using MultipleValued Logic Decision Diagrams to Model System Threat Probabilities, IEEE International Symposium on MulitpleValued Logic (ISMVL), May 2325, 2011, pp. 263267, (with T. Manikas and D.Y. Feinstein).
 A Compliance Framework to Optimize Product Development in a Regulated Industry, Intellectbase International Consortium Academic Conference, March 2526, 2011, (with D.M. Easton).
 Spectral Analysis of Digital Logic Circuit Netlists, International Conference on Computer Aided Systems Theory (EUROCAST), February 611, 2011, pp. 414415.
 Quaternary VoltageMode Logic Cells and FixedPoint Multiplication Circuits, IEEE International Symposium on MulitpleValued Logic (ISMVL), May 2628, 2010, pp. 128133, (with S. Datla).
 Cyber Threat Trees for Large System Threat Cataloging and Analysis, IEEE Systems Conference (SYSCON), April 56, 2010, pp. 610615, (with P. Ongsakorn, K. Turney, S. Nair, S. Szygenda, and T. Manikas).
 Large System Decomposition and Simulation Methodology using Axiomatic Analysis, IEEE International Systems Conference, (SYSCON), April 56, 2010, pp. 223227, (with L. Spenner, P. Krier, S. Nair, S. Szygenda, and T. Manikas).
 An Axiomatic Analysis Approach for LargeScale DisasterTolerant Systems Modeling, International MultiConference on Complexity, Informatics, and Cybernetics (IMIC10), International Conference on Computing, Communications and Control Technologies (CCCT), April 69, 2010, pp. 6670, (best paper award, with T. Manikas, L. Spenner, P. Krier, S. Nair, and S. Szygenda).
 A DigitaltoFrequency Converter using Redundant Signed Binary Addition, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 25, 2009, pp. 495498, (with W. Chen and P. Gui).
 A Low Power High Performance Radix4 Approximate Squaring Circuit, IEEE International Conference on Applicationspecific Systems, Architectures, and Processors (ASAP), July 79, 2009, pp. 9197, (with S. Datla and D.W. Matula).
 On the Guidance of Reversible Logic Synthesis by Dynamic Variable Ordering, IEEE International Symposium on MultipleValued Logic (ISMVL), May 2123, 2009, pp. 132138, (with D. Feinstein).
 Quaternary Addition Circuits Based on SUSLOC VoltageMode Cells and Modeling with SystemVerilog, IEEE International Symposium on MultipleValued Logic (ISMVL), May 2123, 2009, pp. 256261, (with S. Datla, L. Hendrix, and D. Henderson).
 A Low Power Radix4 Dual Recoded Integer Squaring Implementation for use in Design of Application Specific Arithmetic Circuits, IEEE Asilomar Conference on Signals, Systems, and Computers (ASILOMAR), October 2629, 2008, pp. 18191822, (with J. Moore and D.W. Matula).
 Quantum Logic Implementation of Unary Arithmetic Operations, IEEE International Symposium on MultipleValued Logic (ISMVL), May 2223, 2008, pp. 202207, (with L. Spenner, D. W. Matula, and D. M. Miller).
 On the Data Structure Metrics of Quantum MultipleValued Decision Diagrams, IEEE International Symposium on Multiple Valued Logic (ISMVL), May 2223, 2008, pp. 138143, (with D. Y. Feinstein and D. M. Miller).
 Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits, Proceedings of the IEEE/ACM Design, Automation and Test in Europe (DATE), March 1014, 2008, pp. 13781381, (with D. Y. Feinstein and D. M. Miller).
 UML to SystemVerilog Synthesis for Embedded System Models with Support for Assertion Generation, Proceedings of the ECSI Forum on Design Languages, September 1820, 2007, Paper 10 on CDROM, (with L. Li and F. Coyle).
 ESOPbased Toffoli Gate Cascade Generation, Proceedings of the IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, August 2224, 2007, pp. 206209, (with K. Fazel and J.E. Rice).
 Axiomatic Design in the Biomedical Device Industry, Proceedings of the 11^{th} World MultiConference on Systemics, Cybernetics and Informatics (WMSCI), July 811, 2007, (with D. Easton, V.S.S. Nair, and J. Stracener).
 Axiomatic Design Process for Disaster Tolerance, Proceedings of the 11^{th} World MultiConference on Systemics, Cybernetics and Informatics (WMSCI), July 811, 2007, (with D. Easton and V.S.S. Nair).
 Variable Reordering and Sifting for QMDD, IEEE International Symposium on Multiple Valued Logic (ISMVL), May 1416, 2007, electronic proceedings, Session 2B, paper 1, (with D. Michael Miller and D.Y. Feinstein).
 Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL, IEEE International Symposium on Multiple Valued Logic (ISMVL), May 1416, 2007, electronic proceedings, Session 8B, paper 2, (with M. Amoui, D. Grosse, and R. Drechsler).
 Techniques for Disaster Tolerant Information Technology Systems, IEEE Systems Conference, April 912, 2007, pp. 333338, (with C.M. Lawler and S.A. Szygenda).
 Disaster Tolerant Systems Engineering for Critical Infrastructure Protection, IEEE Systems Conference, April 912, 2007, pp. 28, (with M.A. Harper and S.A. Szygenda).
 Performance Evaluation of a Novel Table Lookup Method and Architecture for Integer Functions, IEEE International Conference on Applicationspecific Systems, Architectures, and Processors (ASAP), pp. 99104, September 1113, 2006, (with L. Li, A. FitFlorea, and D.W. Matula).
 A Decision Diagram Package for Reversible and Quantum Circuit Simulation, IEEE Congress on Evolutionary Computation, IEEE World Congress on Computational Intelligence (WCCI), July 1621, 2006, pp. 85978604 on Proceedings CDROM, (best paper of session, with D.M. Miller and D. Goodman).
 QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits, IEEE International Symposium on MultipleValued Logic (ISMVL), May 1720, 2006, pp. 3030 on Proceedings CDROM, (with D.M. Miller).
 A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity ReedMuller Form, IEEE International Symposium on MultipleValued Logic (ISMVL), May 1720, 2006, pp. 3333 on Proceedings CDROM, (electronic version only, with L. Li and M. Perkowski).
 A Digit Serial Algorithm for the Integer Power Operation, ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), April 30May 2, 2006, pp. 302307, (with L. Li and D.W. Matula).
 BDDBased Conjunctive Decomposition Using a Genetic Algorithm and Dependent Variable Affinity, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 2426, 2005, pp. 277280, (with L. Li and S. Szygenda).
 Early Evaluation for Phased Logic Circuits Using BDDs and MVL, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 2426, 2005, pp. 400403, (with K. Fazel and R.B. Reese).
 A Survey and Comparison of Digital Logic Simulators, IEEE MidWest Symposium on Circuits and Systems (MWSCAS), August 710, 2005, p. 156 (abstract), full paper on Proceedings CDROM, (with M. Gunes, F. Kocan, and S.A. Szygenda).
 Disaster Tolerant Computing and Communications, International Conference on Cybernetics and Information Technologies, Systems and Applications (CITSA 2005), and International Conference on Information Systems Analysis and Synthesis (ISAS), July 1417, 2005, pp. 171173, (invited paper, with S. Szygenda).
 IT Application Downtime, Executive Visibility and Disaster Tolerant Computing, International Conference on Cybernetics and Information Technologies, Systems and Applications (CITSA 2005), and International Conference on Information Systems Analysis and Synthesis (ISAS), July 1417, 2005, pp. 165170, (invited paper, with M. A. Harper and C. Lawler).
 Combining Simulation and Formal Verification for Integrated Circuit Design Validation, 9^{th} World MultiConference on Systemics, Cybernetics and Informatics (WMSCI), July 1013, 2005, pp. 9297, (with L. Li and S. Szygenda).
 Lookup Table Structures for Multiplicative Inverses Modulo 2^{k}, IEEE Symposium on Computer Arithmetic (ARITH), June 2729, 2005, pp. 130135, (D.W. Matula and A. FitFlorea).
 The KarhunenLoève Transform of Discrete MVL Functions, IEEE International Symposium on MultipleValued Logic (ISMVL), May 1821, 2005, pp. 194199.
 Hardware Implementation of an Additive BitSerial Algorithm for the Discrete Logarithm Modulo 2^{k}, IEEE Symposium on VLSI (ISVLSI), May 1011, 2005, pp. 130135, (with L. Li, A. FitFlorea, and D.W. Matula).
 A Framework and Process for Curricular Integration and Innovation Using Project Based Interdisciplinary Teams, International Conference on Information Technology (ITCC), April 46, 2005, pp. 432435, (with F.P. Coyle).
 From UML to HDL: a Model Driven Architectural Approach to HardwareSoftware CoDesign, Information Systems: New Generations Conference (ISNG), April 46, 2005, pp. 8893, (with F.P. Coyle).
 Static Variable Ordering in ZBDDs for Path Delay Fault Coverage Calculation, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), July 2528, 2004, pp. I509  I512, (with F. Kocan and M. Gunes).
 Test Vector Generation and Classification Using FSM Traversals, IEEE International Symposium on Circuits and Systems (ISCAS), May 2326, 2004, pp. V309  V312, (with R. Marczynski and S. Szygenda).
 Performance Enhancement in Phased Logic Circuits Using Automatic Slack Matching Buffer Insertion, ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), April 2628, 2004, pp. 413416, (K. Fazel, L. Li, R. B. Reese and C. Traver).
 A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), February 1920, 2004, pp. 3236, (with L. Li and S. Szygenda).
 Spectral Transforms of Mixedradix MVL Functions, IEEE International Symposium on MultipleValued Logic (ISMVL), May 1619, 2003, pp. 329333.
 A CoarseGrain Phased Logic CPU, IEEE International Symposium on Asynchronous Circuits & Systems (ASYNC), May 1216, 2003, pp. 213, (with R. Reese and C. Traver).
 PLFire: A Visualization Tool for Asynchronous Phased Logic Designs, IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), March 37, 2003, pp. 10961097, (poster presentation, with K. Fazel and R. B. Reese).
 A Finegrain Phased Logic CPU, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), February 2021, 2003, pp. 7079, (with R. B. Reese and C. Traver).
 Switching Activity Estimation of FSMs for Low Power Synthesis, IEEE International Symposium on Circuits and Systems (ISCAS), May 2629, 2002, vol. IV, pp. 6568, (with M. Kerttu, P. Lindgren and R. Drechsler).
 Chrestenson Spectrum Computation Using Cayley Color Graphs, IEEE International Symposium on MultipleValued Logic (ISMVL), May 1518, 2002, pp. 123128, (with D. M. Miller and W. Towsend).
 Efficient Adder Circuits Based on a Conservative Reversible Logic Gate, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), April 2526, 2002, pp. 8388, (with J. W. Bruce, L. Shivakumaraiah, P. S. Kokate and X. Li).
 Computing Walsh, Arithmetic and ReedMuller Spectral Decision Diagrams Using Graph Transformations, Great Lakes Symposium on VLSI (GLSVLSI), April 1819, 2002, pp. 178183, (with W. Towsend, D. M. Miller and R. Drechsler).
 Multioutput Timed Shannon Circuits, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 4752, April 2526, 2002, (with R. Drechsler and D. Michael Miller).
 Generalized Early Evaluation in Selftimed Circuits, IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), pp. 255259, March 48, 2002, (with K. Fazel, R. Reese and C. Traver).
 Fast and Efficient Equivalence Checking based on NANDBDDs, IFIP International Conference on Very Large Scale Integration (VLSISOC), pp. 401405, December 35, 2001, (with R. Drechsler).
 Cell Designs for Selftimed FPGAs, IEEE ASIC/SOC Conference (ASIC), pp.175179, September 2001, (with C. Traver and R. Reese).
 Arithmetic Logic Circuits using SelfTimed BitLevel Dataflow and Early Evaluation, IEEE International Conference on Computer Design (ICCD), pp. 1823, September 2326, 2001, ( with R. Reese and C. Traver).
 Application of a Hardware Synthesis Technique for Database Query Optimization, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 2628, 2001, pp. 715718, (with V. Komaragiri and R. Drechsler).
 Evolutionary Algorithm Approach for Symbolic FSM Traversals, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 2628, 2001, pp. 506509, (with R. Drechsler).
 Walsh Spectrum Computations Using Cayley Graphs, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 1417, 2001, pp. 110113, (with W. Towsend).
 Spectral Decision Diagrams Using Graph Transformations, IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), March 1316, 2001, pp. 713717, (with R. Drechsler).
 Low Power Optimization Technique for BDD Mapped Circuits, IEEE/IEICE/ACM Asia South Pacific Design Automation Conference (ASPDAC), January 30February 2, 2001, pp. 615621, (P. Lindgren, M. Kerrtu and R. Drechsler).
 Cache Resident Data Locality Analysis, ACM/IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), August 29September 1, 2000, pp.539546, (with Q. G. Samdani).
 MDDbased Synthesis of MultiValued Logic Networks, IEEE International Symposium for MultipleValued Logic (ISMVL), May 2325, 2000, pp. 4146, (with R. Drechsler and D. Wessels).
 Computation of Spectral Information from Logic Netlists, IEEE International Symposium on MultipleValued Logic (ISMVL), May 2325, 2000, pp. 5358, (with R. Drechsler).
 A Method for Approximate Equivalence Checking, IEEE International Symposium on MultipleValued Logic (ISMVL), May 2325, 2000, pp. 447452, (with R. Drechsler and W. Günther).
 Extracting spectral information from AND/OR representations, IEEE Electrotechnical and Computer Science Conference (ERK), September 2325, 1999, pp. 2732, ( with R. Drechsler and A. Žužek).
 SBDD Variable Reordering Based on Probabilistic and Evolutionary Algorithms, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 2224, 1999, pp. 381387, (with J. P. Williams, R. Drechsler, N. Drechsler and D. Wessels).
 Tradeoff Analysis of Integer Multiplier Circuits Implemented in FPGAs, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 2224, 1999, pp. 301304, (with J. Gaiche and J. Lemieux).
 Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities, IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), presentation poster, March 912, 1999, pp. 758759, (with J. P. Williams, R. Drechsler and N. Drechsler).
 Modified Haar Transform Calculation Using Digital Circuit Output Probabilities, IEEE International Conference on Information, Communications & Signal Processing (ICICS), September 912, 1997, pp. 52  58, (invited paper).
 Applications of Circuit Probability Computation Using Decision Diagrams, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 20  22, 1997, pp. 683687, (with R. P. Moore and J. C. Cordova).
 A Technique for Multiprocessor Memory Resource Estimation, World Multiconference on Systematics, Cybernetics and Informatics, July 711, 1997, Volume 1, pp. 212218, (with J. D. Bullard and D. L. Andrews).
 Graph Analysis and Transformation Techniques for RunTime Minimization in a MultiThreaded Architecture, 30th Hawaii International Conference on Systems Sciences (HICSS), January 1997, Volume 1, pp. 566575, (with D. L. Andrews).
 Behavioral to Structural Translation in ESOP Form Using the Verilog HDL, IEEE International Verilog HDL Conference (IVL), March 1994, pp. 5862, (best paper award with V. S. S. Nair)
 Combinational Logic Synthesis Using Spectral Techniques, IEEE/ACM European Design Automation Conference (EURODAC), September 1993, pp. 358363, (with V. S. S. Nair).
NATIONAL/INTERNATIONAL WORKSHOPS
 Automated Mapping Methods for the IBM Transmon Devices, International Workshop on PostBinary ULSI Systems (ULSIWS), pp. 1217, May 15, 2018, (with K.N. Smith).
 Minimizing Ancilla and Garbage Qubits in Reversible Functions, Southwest Quantum Information and Technology 20th Annual SQuInT Workshop (SQuInT), February 2224, 2018, (with E. Gabrielsen).
 Single Qubit Quantum Ring Structures and Applications, Southwest Quantum Information and Technology 20th Annual SQuInT Workshop (SQuInT), February 2224, 2018, (with K.N. Smith, D.L. MacFarlane, T.P. LaFave, Jr., and W.V. Oxford).
 MUSTANGQ: A Technology Dependent Quantum Logic Synthesis and Compilation Tool, Design Automation for Quantum Computers Workshop, IEEE International Conference on Computer Aided Design (ICCADQCEDA), November 1316, 2017, (refereed abstract and poster presentation, with K.N. Smith).
 On the Computation of ReedMuller Spectra for Cryptography and Switching Theory Applications, Proceedings of the Workshop on Applications of the ReedMuller Expansion in Circuit Design (RMW), May 2425, 2017, (unpublished workshop proceedings, link to abstract only, with D.M. Miller).
 A Vector Space Model for Boolean Switching Networks, Proceedings of the International Workshop on Boolean Problems (IWSBP), September 1719, 2014, pp. 121, (invited talk, link to abstract only, unpublished workshop proceedings).
 On the Relationship of Boolean Function Spectra and Circuit Output Probabilities, Proceedings of the International Workshop on Boolean Problems (IWSBP), September 1719, 2014, pp. 3339, (unpublished workshop proceedings, link to abstract only, with Micah Thornton).
 Mission Planning Analysis using Decision Diagrams (abstract only), Proceedings of the Workshop on Applications of the ReedMuller Expansion in Circuit Design (RMW), May 2425, 2013, pp. 6165, (unpublished workshop proceedings, link to abstract only, with T.W. Manikas and F.R. Chang).
 Direct ReedMuller Transform of Digital Logic Netlists, Proceedings of the Workshop on Applications of the ReedMuller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 2526, 2011, pp. 1120, (with J. Dworak).
 Toffoli Gate Cascade Generation Using ESOP Minimization and QMDDbased Swapping, Proceedings of the Applications of the ReedMuller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 2324, 2009, pp. 6372, (with J. Rice, K. Fazel, K. Kent).
 QMDD and Spectral Transformation of Binary and MultipleValued Functions, 8th International Workshop on Boolean Problems (IWBP), September 1819, 2008, pp. 137144, (with D.M. Miller).
 SystemonChip Power Consumption Refinement and Analysis, Proceedings of the IEEE Dallas Workshop on Circuits and Systems, November 1516, 2007, pp. 8184, (with D. Feinstein and F. Kocan).
 Quantum Logic Circuit Simulation Based on the QMDD Data Structure, Proceedings of the Workshop on Applications of the ReedMuller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 16, 2007, pp. 99105, (with D. Goodman, D.Y. Feinstein, and D.M. Miller).
 ESOP Transformation to Majority Gates for Quantumdot Cellular Automata Logic Synthesis, Proceedings of the Workshop on Applications of the ReedMuller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 16, 2007, pp. 4350, (with D.Y. Feinstein).
 Components of Disaster Tolerant Computing, International Workshop on Information Assurance, in conjunction with the IEEE International Performance Computing and Communications Conference, April 1113, 2007, pp. 380386, (with C.M. Lawler and M.A. Harper).
 Boolean Function Matching Using Walsh Spectral Decision Diagrams, Proceedings of the IEEE Dallas Workshop on Circuits and Systems, October 2930, 2006, pp. 127130, (with J. Moore, K. Fazel and D. M. Miller).
 Discrete Function KL Spectrum Computation over Symmetry Groups of Arbitrary Size, Proceedings of the International Symposium on Representations and Methodology of Future Computing Technologies (formerly, ReedMuller Workshop, RMW05), September 56, 2005,
pp. 110113, (with Lun Li).
 A Standard Cell Implementation of a Phased Logic CPU, Workshop on Token Based Computing, Proceedings of the Workshop on Token Based Computing (ToBaCo), June 22, 2004, pp. 4958, (with R. Reese and C. Traver).
 Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation, International Workshop on SystemonChip for Real Time Applications (SOCRT), July 67, 2002, pp. 400409, (with R. Drechsler, M. Kerttu and P. Lindgren).
 Low Power Optimization Technique for BDD Mapped Finite State Machines, International Workshop on Logic and Synthesis (IWLS), June 47, 2002, pp. 143148, (with M. Kerttu, P. Lindgren and R. Drechsler).
 On Line Error Detection in a Carry Free Adder, International Workshop
on Logic and Synthesis (IWLS), June 47, 2002, pp. 251254, (with W. Towsend and P.K. Lala).
 Transformations Amongst the Walsh, Haar, Arithmetic and ReedMuller Spectral Domains, International Workshop on Applications of the ReedMuller Expansion in Circuit Design (RMW), August 1011, 2001, pp. 215225, (with D. M. Miller and R. Drechsler).
 Arithmetic Logic Circuits using SelfTimed BitLevel Dataflow and Early Evaluation, International Workshop on Logic and Synthesis (IWLS), June 1215, 2001, pp. 7277, (with R. Reese and C. Traver).
 Low Power Optimization Technique for BDD Mapped Circuits, International Workshop on Logic Synthesis (IWLS), May 31June 2, 2000, pp. 221230, (with P. Lindgren and M. Kerttu).
 Probabilistic Equivalence Checking Using Partial Haar Spectral Diagrams, International Workshop on Applications of the ReedMuller Expansion in Circuit Design (RMW), August 1999, pp. 123132, (with R. Drechsler and W. Günther).
 Logic Synthesis Based on the Structure of an Ordered DD, International Workshop on Logic Synthesis (IWLS), July 1999, pp. 2125, (with D. M. Wessels).
 Integration of CAD Tools and Structured Design Principles in an Undergraduate Computer Engineering Curriculum, Workshop on Computer Architecture Education, International Symposium on Computer Architecture (ISCA), June 1998, (with D. L. Andrews).
 Multiprocessor Resource Estimation Using a Stochastic Modeling Approach, Symposium on Parallel and Distributed Processing, Workshop on Resource Estimation (SPDP), October 1996, (with D. L. Andrews and J. D. Bullard).
 Fast ReedMuller Spectrum Computation Using Output Probabilities, Workshop on Applications of the ReedMuller Expansion in Circuit Design (RMW), August 1995, pp. 281  287, (with V. S. S. Nair).
 Parity Function Detection and Realization Using a Small Set of Spectral Coefficients, IEEE/ACM International Workshop on Logic Synthesis (IWLS), May 1995, pp. 839  847, (with V. S. S. Nair).
 A Numerical Method for ReedMuller Circuit Synthesis, Workshop on Applications of the ReedMuller Expansion in Circuit Design (RMW), September 1993, pp. 6974, (with V. S. S. Nair).
REGIONAL CONFERENCES
 Teaching a Laboratory Intensive Class in a Distance Education Mode, ASEE 2008 Midwest Section Conference, September 1819, 2008, (with J. Moore and R.W. Skeith).
 Perl for Introductory Programming Classes, ASEE 2007 Midwest Section Conference, September 1921, 2007, (with J. Moore and R.W. Skeith).
 Prefix Parallel Adder Virtual Implementation in Reversible Logic, IEEE Region 5 Technical Conference, April 2022, 2007, pp. 7480, (with D.Y. Feinstein and V.S.S. Nair).
 Multilevel Variable Length Shifter Design for an Iterated ShiftandAdd Product Operation , IEEE Region 5 Technical Conference, April 2022, 2007, pp. 234238, (with J. Moore and D.W. Matula).
 Encouraging Computer Engineering Students to Take the Fundamentals of Engineering (FE) Examination, ASEE 2006 Midwest Section Conference, September 15, 2006, on Proceedings CDROM, (with J. Moore and R. W. Skeith).
 An Undergraduate Course in Perl: An All Purpose Programming Language, ASEE Midwest Section Conference, September 1416, 2005,
on Proceedings CDROM, (with J. Moore and R.W. Skeith).
 A Modular and Specifications Oriented Digital Circuit Design Laboratory, ASEE Midwest Section Conference, September 29October 1, 2004, (with J. Moore and R. W. Skeith).
 Research Results in Equivalence Checking, NSF Design, Service and Manufacturing Grantees and Research Conference, January 58, 2004, (with A. Mukherjee).
 UNIX Scripting and Highlevel Language Education Using an Emulator, ASEE Midwest Section Conference, September 2002, (with R. W. Skeith).
 Learning and Using UNIX on a MS Windows© Based Computer, Memphis Area Engineering and Sciences Conference (MAESC), May 10, 2002, p. 36, (with R. W. Skeith).
 Computation of Disjoint Cube Representations Using a Maximal Binate Variable Heuristic, IEEE Southeastern Symposium on System Theory, March 1819, 2002, pp. 417421, (with L. Shivakumaraiah).
 Partial Binary Decision Diagrams , IEEE Southeastern Symposium on System Theory, March 1819, 2002, pp. 422425, (with W. Towsend).
 Odd/Even Cube Covering for Minimizing ESOP Circuits, IEEE Southeastern Symposium on System Theory, March 2000, pp. 274278, (with B. Q. Vu and R. Drechsler).
 Performance Evaluation of a Data Driven Architecture, 1996 Arkansas Computer Conference, March 1996, pp. 7176.
ARTICLES, INTERVIEWS, OPINION PIECES AND MEDIA
 This could change everything: Bills would boost research into radically new way of computing, Dallas Morning News, Editorial, August 7, 2018, (authored by editorial board member Michael Lindenberger, including M.A. Thornton's research efforts in quantum computing at SMU).
 Licensure and Certification: Two Different Forms of Professional Credentials, ME Today, July 2014, (reprint of IEEEUSA Today's Engineer article in the mechanical engineering society ASME publication, ME Today).
 Licensure and Certification: Two Different Forms of Professional Credentials, IEEEUSA Today's Engineer, May 2014.
 The Path to Licensure, PE The Magazine for Professional Engineers, published by the NSPE, October 2012, p. 2427, (authored by D. Boykin, with quotes from interview of M. A. Thornton).
 Intellectual Property Engineering Consulting and Professional Licensure, IEEEUSA Today's Engineer, (October 2011).
 Internet Searches Reveal Bounty of Personal Information, DallasFort Worth KXAS, Channel 5, NBC affiliate, local news interview aired on August 25, 2011, (reported by Kimberly King with interview of M.A. Thornton), video.
 State Fined Company Named in FBI Search Warrants, DallasFort Worth KTVT, Channel 11, CBS affiliate, local news interview aired on August 23, 2011, (reported by Jack Fink with interview of M.A. Thornton), video.
 When do Software Systems need to be Engineered?, IEEEUSA Today's Engineer, July 2011, (with P.A. Laplante).
 Should You Take the Computer Engineering PE Exam or the Electrical and Electronics Engineering PE Exam?, IEEEUSA Today's Engineer, April 2011, (with A. Collins).
 IEEEUSA and IEEE Computer Society Cooperate in New Professional Software Engineering Licensure Initiative (full version), IEEEUSA Today's Engineer, January 2011, (with P.A. Laplante).
 IEEEUSA and IEEE Computer Society Cooperate in New Professional Software Engineering Licensure Initiative (shortened version), IEEEUSA in ACTION, December 2010, pp. 78, (with P. A. Laplante).
 Potential Change Slated for PE Educational Requirements, IEEEUSA Today's Engineer, June 2010, (with S.F. Barrett and D.L. Whitman).
 Why Should You Become a Licensed Professional Engineer?, IEEEUSA Today's Engineer, February 2010.
 Smart Meters can be Hacked: Security Experts, DallasFort Worth KXAS, Channel 5, NBC affiliate, local news interview aired on Sept. 20 and 21, 2009, (anchored by Ken Kalthoff with interviews of M.A. Thornton and V.S. Nair), video.
 Software Engineering PE Examination Development Approved, IEEEUSA Today's Engineer, September 2009.
 Why Computer Engineering Students Should Take the Fundamentals of Engineering Examination and How Professors can Help, IEEEUSA Today's Engineer, June 2009, (with J. Moore and R. W. Skeith).
 Is It Time to License Software Engineers?, PE The Magazine for Professional Engineers, published by the NSPE, December 2007, p. 2629, (authored by D. Boykin, with quotes from interview of M. A. Thornton).
 Criteria 2000  The New Game  How Does it Play Out, ChAPTER One Online Magazine, Student magazine of the AIChE, September 1998, vol. 1, no. 1, (with R. E. Babcock and R. W. Skeith).
ABSTRACTS
 An Opensource General Compiler for Quantum Computers, Free and Open Source Developers European Meeting (FOSDEM), February 3, 2019, (with K.N. Smith).
 Single Qubit Quantum Ring Oscillator and Applications for Storage and True Random Number Generation, Quantum Simulation & Computation Conference (QSC), February 1216, 2018, (poster, with W.V. Oxford, D.L. MacFarlane, and T.P. LaFave, Jr.).
 Design and Implementation of a Photonic Quantum Storage Device, IBM Think Q Conference, December 68, 2017, (poster, with William V. Oxford, James S. Gable, Duncan L. MacFarlane, and Timothy P. LaFave, Jr.).
 Single Photon Quantum State Oscillator, poster, NIST Single Photon Worksop (SPW), July 31  August 4, 2017,p. 140, (with D.L. MacFarlane, T.P. LaFave, Jr., and W.V. Oxford).
 Sample Size Calculations using Techniques from Power Analysis, poster, ASA Conference on Statistical Practice (CSP), February 20, 2016, p. 27, (with M.A. Thornton, J. Rendon, and G. Pham).
 Use of Hamming Weights Instead of Uniform Distributions to Analyze a Set of Strings for Randomness, poster, ASA Conference on Statistical Practice (CSP), February 20, 2016, p. 27, (with J. Rendon, M.A. Thornton, and G. Pham).
 Setting the Stage for CE2016: A Revised Body of Knowledge, Frontiers in Education Conference (FIE), Oct. 2225, 2014, (workshop cofacilitator, with E. Durant, J. Impagliazzo, S. Conroy, R.B. Reese, H. Lam, and V. Nelson).
 Computer Engineering Curriculum Guidelines PreConference Workshop, Frontiers in Education Conference, October 2326, 2013, p. 1, (workshop cofacilitator, with E. Durant, S. Conroy, J. Impagliazzo, A. McGettrick, and T. Wilson).
 Special Session: CE2004 Revisions (Computer Engineering Curriculum Guidelines) Special Session, Frontiers in Education Conference (FIE), October 36, 2012, (with E.Durant, S. Conroy, J. Impagliazzo, A. McGettrick, and T. Wilson).
 Computer Engineering Review Task Force Report, Panel Presentation, ACM SIGCSE Technical Symposium on Computer Science Education (SIGCSE), February 29March 3, 2012, pp. 401402, (panelist, with J. Impagliazzo, moderator, S. Conroy, E. Durant, A. McGettrick, and T. Wilson).
 Axiomatic Analysis and Cyber Threat Tree Models for the Development of LargeScale DisasterTolerant Information Security Systems, Raytheon Information Systems and Computing Technology Network Symposium (ISaCTN), April 21, 2010, (with T. Manikas).
 Advances in Quantum Computing Fault Tolerance and Testing, IEEE High Assurance Systems Engineering Symposium (HASE), November 1416, 2007, pp. 369370, (with D. Y. Feinstein and V.S.S. Nair).
 A Second Undergraduate Course in Digital Logic Design: The Datapath+Controllerbased Approach, ASEE 2003 Southeastern Section Conference, April 2003, (with A. S. Collins).
 UNIX and Highlevel Language Education Using Windows Operating Systems, ASEE 2001 Southeastern Section Meeting, April 2001, (with R. W. Skeith).
 Binary Decision Diagram Visualization: A Research Experience for Undergraduates, ASEE ThirtyFourth Midwest Section Conference, April 1999, (with R. W. Skeith, S. M. Karp, J. N. Taylor).
 Integration of CAD Tools and Structured Design Principles in an Undergraduate CE Curriculum, IEEE Computer Architecture Technical Committee Newsletter, February 1999, pp.89, (with D. L. Andrews).
 Assessment Analysis in Criteria 2000, ASEE ThirtyThird Midwest Section Conference, April 1998, (with R. W. Skeith).
 Integration of Hardware Description Languages into an Undergraduate Design Laboratory Course, ASEE ThirtyFirst Midwest Section Conference, April 1996.
TECHNICAL REPORTS
 An Overview of Placement and Routing Algorithms for PCB, VLSI, and MCM Designs with a Proposal for a New MCM Routing Algorithm, Technical Report, Dept. of Computer Systems Engineering, University of Arkansas, Fayetteville, Arkansas, 1996, (written by C. N. Frisbee, directed by M. A. Thornton).
 Iterative Combinational Logic Synthesis Techniques Using Spectral Data, Technical Report, Southern Methodist University, CSE9208, 1992 (with V. S. S. Nair).
 Applications and Efficient Computation of Spectral Coefficients for Digital Logic, Technical Report, Southern Methodist University, CSE9413, 1994, (with V. S. S. Nair).
 Boolean Function Spectrum Computation Using a Structural Representation, Technical Report, Southern Methodist University, CSE9440, 1994, (with V. S. S. Nair).
 ReedMuller Circuit Synthesis Using Numerical Methods, Technical Report, Southern Methodist University, CSE9319, 1993, (with V. S. S. Nair).
DISSERTATIONS/THESES
 Implementation of Switching Function Circuit Models as Vector Space Transformations, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, December 16, 2017, (written by David Kebo Houngninou, directed by M.A. Thornton).
 Ransomware Detection using Machine Learning and Physical Sensor Data, M.S.C.p.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, December 16, 2017, (written by Michael A. Taylor, directed by M.A. Thornton).
 Demographic Group Prediction Based on Smart Device User Recognition Gestures, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, April 26, 2017, (written by Adel Alharbi, directed by M.A. Thornton).
 Automated Detection of Submerged Navigational Obstructions in Freshwater Impoundments with Hull Mounted Sidescan Sonar, M.S.C.p.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, July 8, 2015, (written by P. Morris, directed by M.A. Thornton).
 Specialized Multiplier Circuits, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, December 4, 2014, (written by J. Moore, directed by M.A. Thornton).
 A Fixedpoint DigitSerial Squaring Algorithm using an Arbitrary Number System, M.S.C.p.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, August 3, 2012, (written by Saurabh Gupta, directed by M.A. Thornton).
 A Global MultipleValued Clock Approach for HighPerformance MultiPhase Clock Integrated Circuits, M.S.C.p.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, December 2, 2011, (written by Rohit Menon, directed by M.A. Thornton).
 ADBP, A Novel Approach to Business Process Design in a Regulated Industry, Ph.D. dissertation, Dept. of Applied Science, Southern Methodist University, April 21, 2011, (written by Diana Easton, directed by M.A. Thornton).
 Securing Unfamiliar Entry Points Against Faulty User Authentication Via Electromagnetic Side Channel Attacks, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 27, 2010, (written by John J. Howard, directed by M.A. Thornton).
 Design and Validation of Quaternary Arithmetic Circuits, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, December 4, 2009, (written by Satyendra Datla, directed by M.A. Thornton).
 ComputerAidedDesign Methods for Emerging Quantum Computing Techniques, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, April 18, 2008, (written by David Feinstein, directed by M.A. Thornton).
 Quantum Logic Implementation of Unary Arithmetic Operations with Inheritance, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 24, 2008, (written by Laura Spenner, directed by M.A. Thornton).
 Hardware Acceleration of Software Library String Functions, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, December 2007, (written by P. Kulkarni, directed by M.A. Thornton).
 An Automated Tool for HDL and Configuration File Generation from UML System Descriptions, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, June 2007, (written by K. Hawkins, directed by M.A. Thornton).
 A Quantum Logic Simulator Based on Decision Diagrams, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 2007, (written by D. Goodman, directed by M.A. Thornton).
 Integrated Techniques for the Formal Verification and Validation of Digital Systems, Ph.D. dissertation, Dept. of Computer Science and Engineering, Southern Methodist University, May 2006, (written by Lun Li, directed by M. A. Thornton)
 Crosstalk Delay Analysis in Very Deep Submicron VLSI Circuits, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 2004, (written by Satyendra Datla, directed by M. A. Thornton).
 Performance Enhancement Techniques for Phased Logic Circuits, M.S.Cp.E. thesis, Dept. of Computer Science and Engineering, Southern Methodist University, April 2004, (written by Kenneth B. Fazel, directed by M. A. Thornton).
 Application of Decision Diagrams for Information Storage and Retrieval, M.S.E.E. thesis, Dept. of Electrical and Computer Engineering, Mississippi State University, May 2002, (written by Vivek Komarigiri, directed by M. A. Thornton).
 ESOP Circuit Minimization Based on the Function OnSet, M.S.E.E. thesis, Dept. of Electrical and Computer Engineering, Mississippi State University, August 2000, (written by Likai Chai, directed by M. A. Thornton).
 A Split Data Cache Organization Based on Runtime Data Locality Estimation, Ph.D. dissertation, Dept. of Computer Science and Computer Engineering, University of Arkansas, May 2000, (written by Quazi Galib Samdani, directed by M. A. Thornton).
 An FPGA Approach for SNR Estimation Using PhaseOnly Data, M. S. C. S. E. Thesis, Dept. of Computer Systems Engineering, University of Arkansas, August 1999, (written by Pramodini Arramreddy, directed by M. A. Thornton).
 A BDD Variable Reordering Heuristic Based on Output Probability Periodicity, M. S. C. S. E. Thesis, Dept. of Computer Systems Engineering, University of Arkansas, Fayetteville, Arkansas, December 1998, (written by Joshua P. Williams, directed by M. A. Thornton).
 Probability Based Variable Ordering and Reordering Heuristics for Decision Diagrams, M. S. C. S. E. Thesis, Dept. of Computer Systems Engineering, University of Arkansas, Fayetteville, Arkansas, August 1997, (written by Roger P. Moore, directed by M. A. Thornton).
 Implementation of Compiler, Viewer, and Parallelism Analysis Software for the IF1 Language, M. S. E. Thesis, Dept. of Computer Systems Engineering, University of Arkansas, Fayetteville, Arkansas, December 1996, (written by Suwanto, directed by M. A. Thornton).
 Spectral Based Numerical Methods for Combinational Logic Synthesis, Ph.D. dissertation, Department of Computer Science and Engineering, Southern Methodist University, August 4, 1995.
