Verilog - Cadence Xcelium

Verilog is a hardware description language (HDL) for developing and modeling circuits. The Cadence Xcelium tool will help you simulate circuits that have been developed in Verilog.

Basic Xcelium Tutorial

For this tutorial, the results will be displayed on a console. Therefore, the Xcelium tool may be used in your X-windows emulator or console window (e.g., Putty).

Use the following files for this tutorial:

half_adder.v Verilog file that implements a half-adder circuit
half_adder_tb.v Testbench file to test the half-adder circuit

To run the Verilog program using these files, use the command: xmverilog half_adder.v half_adder_tb.v

The program will print the results on the console. The results will also be written to the xmverilog.log file.

To exit the program, use the command: exit

Verilog Language Help

SMU Resources

There is an e-book available to SMU students from the SMU library site: http://smu.edu/libraries/.

Do a "Quick Search" on the "Library Catalog" title "Design through Verilog HDL". This will get you the e-book by T.R. Padmanabhan, which is an introductory text on Verilog. Click on the "Linked Resources" link at the bottom.

Note: if you are connecting to the library site from off-campus, you will need to enter information from your SMU ID card for authentication before you will be allowed access to the e-book.

Web Resources

If you are looking for short tutorials on the basics of Verilog, the following web links may be helpful:

Developing Verilog Testbenches

After you have developed your Verilog system modules, you will need to develop "testbench" modules to test your system modules. A useful tutorial for developing Verilog testbenches is the following:

Verilog Tutorial: Practical Coding Style for Writing Testbenches (PDF) (from W. Gibb and T. Farmer, George Washington U.)

Advanced Topics - Generating Waveforms using SimVision

For timing analysis of circuits, Xcelium can generate waveforms for Verilog circuits using the SimVision package. A tutorial for using this package can be found here: SimVision_Tutorial_2022Mar.pdf .

SimVision will display graphics with waveforms, so you will need to run Xcelium in your X-windows emulator in order to use the SimVision package.

Use the following files for this tutorial:

ex3.v Verilog file that implements a simple logic circuit with gate delays
ex3_tb_wave.v Testbench file to test the simple logic circuit

T. Manikas Last update 2022 Mar 22