Fall 2016 Mon-Wed 2:00 PM - 3:20 PM Location: Caruth Hall 0379
CSE 3381 Digital Logic Design Lab (Required Laboratory)
Fall 2016 Section N11 Wed 12:00-1:50PM Junkins 215
Fall 2016 Section N14 Mon 5:00PM-6:50PM Junkins 215
Mitch Thornton, 481 Caruth Hall, email@example.com
Mon, Wed, 12:30PM-1:50PM in 481 Caruth Hall or by email appointment
Students needing academic accommodations for a disability must first be registered with Disability Accommodations & Success Strategies (DASS) to verify the disability and to establish eligibility for accommodations. Students may call 214-768-1470 or visit http://www.smu.edu/alec/dass.asp to begin the process. Once registered, students should then schedule an appointment with the professor to make appropriate arrangements.
Religiously observant students wishing to be absent on holidays that require missing class should notify their professors in writing at the beginning of the semester, and should discuss with them, in advance, acceptable ways of making up any work missed because of the absence. (See University Policy No. 1.9.)
EXCUSED ABSENCES FOR UNIVERSITY EXTRACURRICULAR ACTIVITIES
Students participating in an officially sanctioned, scheduled University extracurricular activity should be given the opportunity to make up class assignments or other graded assignments missed as a result of their participation. It is the responsibility of the student to make arrangements with the instructor prior to any missed scheduled examination or other missed assignment for making up the work. (See the University Undergraduate Catalog).
CSE 3381 CO-REQUISITE LAB INSTRUCTOR/TEACHING ASSISTANT
Section N11, John Politz, firstname.lastname@example.org
Section N14, John Politz, email@example.com
LAB INSTRUCTOR OFFICE HOURS
To be announced in lab, and by email appointment
TEXTS AND LAB EQUIPMENT (ALL 3 ARE REQUIRED)
Digital Design using Digilent FPGA Boards, Verilog/Active-HDL Version, (MUST BE THE VERILOG VERSION NOT THE VHDL VERSION!!), Richard E. Haskell and Darrin M. Hanna, LBE Books, 2009, ISBN-978-0-9801337-7-6.
Introduction to Digital Design using Digilent FPGA Boards Block Diagram/Verilog Examples, (MUST BE THE VERILOG VERSION NOT THE VHDL VERSION!!), Richard E. Haskell and Darrin M. Hanna, LBE Books, 2009, ISBN-978-0-9801337-9-0.
Digilent BASYS2 Spartan-3E FPGA Board, this is a circuit board that you will bring to lab and use to do experiments.
Digital Design, 5th Edition, M. Morris Mano and Michael D. Ciletti, Pearson Prentice-Hall, 2013, ISBN-10: 0-13-277420-8, ISBN-13: 9780132774208.
Introduction to Logic Synthesis Using Verilog, R. B. Reese and M. A. Thornton, Morgan & Claypool Publishers, 2006, ISBN 10-1598291068.
Covers the history of logic and its application to digital switching circuitry. Topics include algebraic, combinational, and sequential circuitry. Emphasizes programmable logic and hardware description languages for modeling, synthesis, and simulation. Introduces the controller plus datapath architecture present in the majority of modern information processing circuits. Requires a weekly corequisite laboratory.
1. CSE 2240 - Assembly Language Programming and Machine Organization (Grade of C- or better).
2. CSE 2353 - Discrete Computational Structures (Grade of C- or better).
3. Or, in lieu of above, permission of Instructor.
HISTORIC TTL DEVICE DATASHEETS
National Semiconductor (local)
IC Fabrication, 38:30, (.avi, .mp4, .wmv)
MOSFETs, 8:27, (.avi, .mp4, .wmv)
CMOS Logic Gates, 8:47, (.avi, .mp4, .wmv)
TOPICS AND LEARNING OUTCOMES
- Number Systems and Codes
- Binary, Octal, Hexadecimal
- Base Conversions
- Complements and Arithmetic Signs
- ASCII, BCD, Gray, and Parity
- Storage and Logic at the Register Transfer Level
- Registers and RTL
- Logic Operations
- Boolean Algebra
- Axioms, Theorems, and Properties
- Canonical and Standard Forms
- Logic Gates/Operators
- Positive and Negative Logic
- Integrated Circuits and Families
- Combinational Gate-Level Minimization
- Map Method
- Two-level and Multi-level Circuits
- Verilog HDL Introduction
- Discrete Event Simulation
- Modules and Primitives
- Combinational Logic Building Blocks
- Adders, Subtractors, and Comparators
- Encoders and Decoders
- Multiplexers and Demultiplexers
- Verilog HDL for Combinational Logic/Datapaths
- Synchronous Sequential Logic
- Latches and Flip-flops
- Characteristic Tables and Equations
- Timing Diagrams
- State Equations, Tables, and Diagrams
- Mealy and Moore Models and HDL Descriptions
- State Reduction and Assignment
- Excitation Tables and FSM Synthesis
- Verilog Descriptions for Controllers
- Specialized and Common Circuits: Registers and Counters
- Parallel and Serial I/O
- Verilog HDL for Registers and Counters
- Memory and Introduction to Programmable Logic
- RAM and ROM Structure
- Address Decoding
- Programmable Logic Structures
- Timing Diagrams
- Register Transfer Level (RTL) System Descriptions
- Basic Notation
- RTL in Verilog HDL