ECE  5/7387  Digital Systems Design
Fall 2019      Mon-Wed 11:00AM-12:20PM     Location: 183 Caruth Hall
Laboratory    Sections:
                     N11C    Fri        8:00-9:50AM        Location: 215 Junkins
                     N12C    Mon     9:00-10:50AM      Location: 215 Junkins
                     N13C    Wed     3:00-4:50PM         Location: 215 Junkins
                     N14C    Distance Students Only -  No on-campus Laboratory meeting
                     N15C    Fri       10:00-11:50AM     Location: 217 Junkins

CLASS INSTRUCTOR
Mitch Thornton, 328 Junkins, mitch@smu.edu

OFFICE HOURS
MW 10:00AM-10:50AM in 328 Junkins or by email appointment
 
7387 GRADUATE VERSION OF CLASS
Students enrolled in the graduate version of this class will have additional requirements to meet in the assigned coursework including laboratory experiments, design projects, examinations, and written assignments.

DISABILITY ACCOMMODATIONS
Students needing academic accommodations for a disability must first register with Disability Accommodations & Success Strategies (DASS). Students can call 214-768-1470 or visit http://www.smu.edu/Provost/SASP/DASS to begin the process. Once approved and registered, students will submit a DASS Accommodation Letter to faculty through the electronic portal DASS Link and then communicate directly with each instructor to make appropriate arrangements. Please note that accommodations are not retroactive and require advance notice to implement.

RELIGIOUS OBSERVANCE
Religiously observant students wishing to be absent on holidays that require missing class should notify their professors in writing at the beginning of the semester, and should discuss with them, in advance, acceptable ways of making up any work missed because of the absence. (See University Policy No. 1.9)

EXCUSED ABSENCES FOR UNIVERSITY EXTRACURRICULAR ACTIVITIES
Students participating in an officially sanctioned, scheduled University extracurricular activity should be given the opportunity to make up class assignments or other graded assignments missed as a result of their participation. It is the responsibility of the student to make arrangements with the instructor prior to any missed scheduled examination or other missed assignment for making up the work. (See 2018-2019 University Undergraduate Catalogue).

LAB INSTRUCTOR/TEACHING ASSISTANT
TBD

LAB INSTRUCTOR OFFICE HOURS
To be announced in lab and by email appointment
 
TEXT
Introduction to Logic Synthesis Using Verilog HDL, Robert B. Reese and Mitchell A. Thornton, Morgan & Claypool Publishers , 2006, ISBN 10-1598291076 (errata).
Finite State Machine Datapath Design, Optimization, and Implementation, Justin Davis and Robert B. Reese, Morgan & Claypool, 2008, ISBN 1-59829-529-2.

SOFTWARE
Download the Quartus Prime Lite software from the Intel Website HERE. (Please do NOT download and install until after we have discussed the software in class)

REFERENCE
Fundamentals of Digital Logic with Verilog Design, 3rd Edition, Stephen Brown and Zvonko Vranesic, Mc-Graw-Hill, 2014, ISBN 0-07-338054-7.
HDL Chip Design, Douglas J. Smith, Doone Publications, 5th Edition, 1996, ISBN 0-9651934-3-8.

CATALOG DESCRIPTION
Modern topics in digital systems design including the use of HDLs for circuit specification and automated synthesis tools for realization.  Programmable logic devices are used throughout the course.  This course has heavy laboratory assignment content and a design project.

CO-REQUISITE
Digital Systems Design Laboratory Enrollment

PREREQUISITES
ECE 2381 Digital Computer Logic (or CS 3381 Digital Logic Design)

VIDEOS
IC Fabrication, 38:30, (.avi, .mp4, .wmv)
PN Junctions, 10:36, (.avi, .mp4, .wmv)
MOSFETs, 8:27, (.avi, .mp4, .wmv)
CMOS Logic Gates, 8:47, (.avi, .mp4, .wmv)
Packaging, 5:35, (.avi, .mp4, .wmv)

ADMINISTRATION
Class Schedule
Grading Policy (Grading Policy Acknowledgement Form)

TOPICS

• Digital Logic Design Review
• HDL (Discrete Event) Simulators
• Verilog Hardware Description Language (HDL)
• Combinational Logic Synthesis using Verilog
• Programmable Logic Architecture and LPMs
• Timing Constraints and Timing Models in Programmable Logic
• Pipelining for Increased Throughput
• Sequential Logic Synthesis using Verilog
• FSM State Assignment
• High Level Synthesis