RTL Compiler - Synopsys Design Compiler

After you have simulated and verified that your Verilog code is working properly, you can compile the Verilog modules to produce a circuit that is optimized for various criteria (area, timing, power). The Synopsys Design Compiler (SDC) is available on the Lyle machines. Set up X-Windows access as you did for the Cadence Verilog tool to run SDC.

A useful tutorial to get started is the following:

• Synopsys Tutorial: Using the Design Compiler (PDF) (from T. Farmer and W. Gibb, GWU)
• Tutorial Addendum for SMU students (PDF). This document contains additional information specific to SMU users - please use with the GWU tutorial. (UPDATED 12/9/20)

• .synopsys_dc.setup
• osu05_stdcells.v
• osu05_stdcells.db
• halfadder.v
• fulladder.v
• fulladder_tb.v

Tool Tips

To save an image of the current window or active view

1. Choose View > Save Screenshot As. The Save Screenshot As dialog box appears.
2. Select the file, or enter the path and file name in the "File name" box. The default format is PNG. You can specify a different format by using its extension to the file name.
3. To save an image of the active view window instead of the top-level GUI window in which you are working, select the "Grab screenshot of active view only" option.
4. Click Save.